Integrert krets med flaggregister til bruk i seleksjon av permanente celler i volumoperasjoner

Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state. The use of a flag register allows simplification of the instruction set to register load instructions and basic bulk operation instructions (and a flow through operation using a serial output from the registers), while providing a wide variety of possible block selections for the different bulk operations.