Digital DQPSK dekoder delkrets

A digital DQPSK decoder circuit element is useful for separating phase difference data (dp) from multidigit phase data (dd) present with the original data rates of DPSK data pairs (dp). Said element comprises a first constant adder (k1) to which the digital word (''45 DEG '') corresponding to the phase angle 45 DEG and the phase data (dd) are supplied; an adder (sm) whose first input is located at the output of the constant adder (k1); a subtractor (s1) whose subtrahend input is connected to the output of the adder (sm); a subtractor (s2) at whose output the phase differences (dp) can be taken; a delay element (v) whose delay time is equal to the period of the data rate and whose output is located at the subtrahend input of the subtractor (s2); and a second constant adder (k2) to which the digital word (''45 DEG '') corresponding to the phase angle (45 DEG ) is supplied. The minuend input of the subtractor (s2), the delay element (v) and the constant adder (k2) are supplied with the highest digit (mb) of the output signal from the adder (sm), and the low pass (tp) is connected, as a PLL loop filter, via the output of the subtractor (s1) to the second input of the adder (sm).