SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate...

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Hauptverfasser:	LEONARD GULER, MAKRAM ABD EL QADER, CHANAKA MUNASINGHE, PRATIK PATEL, ANINDYA DASGUPTA, REZA BAYATI, SIKANDAR ABBAS, MADELEINE STOLT
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	LEONARD GULER MAKRAM ABD EL QADER CHANAKA MUNASINGHE PRATIK PATEL ANINDYA DASGUPTA REZA BAYATI SIKANDAR ABBAS MADELEINE STOLT
description	Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS
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