INPUT BIAS CIRCUIT FOR BUFFER AMPLIFIER

An input bias circuit comprising a first impedance cir- cuit (D1, D2) having a first impedance, said first impedance circuit (D1, D2) comprising a first and a second node, a second impedance circuit (D3, D4) having a second impedance, said sec- ond impedance circuit (D3, D4) comprising a first and a second node, wherein the first node is operatively connected to the second node of first impedance circuit (D1, D2). The first and second impedance circuits (D1, D2), (D3, D4) each comprises one or more semiconductor devices (D1, D2, D3, D4) characterised in that the first and second impedance circuits (D1, D2), (D3, D4) are connected in series, and in that the first and second imped- ance circuits (D1, D2), (D3, D4) each provides the characteris- tic of a pair of anti-parallel diodes.