INTEGRATED CIRCUIT PACKAGE HAVING PIN UP INTERCONNECT

The present invention relates to an integrated circuit package and manufacturing method thereof, and more particularly to a integrated circuit package having pin up conductive plating to form an interconnect, where an opening on the patterned fifth layer photo-resist material located at bottom porti...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	YUAN LINHUI, LOW LOKE CHEW
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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