SYSTEM FOR INCREASING THROUGHPUT FOR MEMORY DEVICE

THE PRESENT INVENTION PROVIDES A SYSTEM FOR INCREASING THE THROUGHPUT FOR A MEMORY SUBSYSTEM, IN PARTICULAR ON THAT INCLUDES A PIPELINED MEMORY DEVICE AND A NON-CACHED SINGLE-BUS PROCESSOR CORE. WITH THIS SYSTEM, TOTAL LATENCY OF THE MEMORY SUBSYSTEM IS REDUCED AND THUS THROUGHPUT IS INCREASED, SAID CONDITION IS ACHIEVED WITH THE INTRODUCTION OF A PLURALITY OF BUFFER UNITS, PREFERABLY AT LEAST TWO SLIDING BUFFERS WITHIN THE MEMORY CONTROLLER OF THE PRESENT INVENTION. SAID PLURALITY OF BUFFER UNITS IS CONFIGURED TO CAPTURE SPECULATIVE READS, THEREBY AVOIDS LATENCY IN THE MEMORY DEVICE. MOST ILLUSTRATIVE DRAWING: