A FREQUENCY DIVIDER

THERE IS DISCLOSED A FREQUENCY DIVIDER (900), COMPRISING: A CLOCK INPUT ADAPTED TO RECEIVE A CLOCK SIGNAL; A RESET INPUT ADAPTED TO RECEIVE A RESET SIGNAL; A DIVISION CIRCUIT (30, 40) ADAPTED TO DIVIDE THE CLOCK SIGNAL BY A FACTOR TO PRODUCE AN OUTPUT SIGNAL; AN OUTPUT ADAPTED TO OUTPUT THE OUTPUT SIGNAL, AND A CLOCK DISABLE CIRCUIT (70) CONNECTED TO THE RESET INPUT AND THE CLOCK INPUT. THE CLOCK DISABLE CIRCUIT (70) IS CONTROLLED BY THE RESET SIGNAL TO DISABLE THE CLOCK SIGNAL TO THE DIVISION CIRCUIT (30, 40). A SETTING CIRCUIT (10, 20) IS CONNECTED TO THE RESET INPUT AND THE OUTPUT. THE SETTING CIRCUIT (10, 20) IS CONTROLLED BY THE RESET SIGNAL TO SET THE OUTPUT SIGNAL TO A DESIGNATED STATE.