PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS

PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS

THERE IS DISCLOSED A CIRCUIT ADAPTED TO EXHIBIT DIODE CHARACTERISTICS. THE CIRCUIT COMPRISES: A DIODE INPUT NODE (120);•A DIODE OUTPUT NODE (130);•A GATE BIAS SUB-CIRCUIT (155) HAVING A GATE BIAS NODE (170), THE GATE BIAS SUB-CIRCUIT (155) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120) AND ADA...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: SYAHRIZAL SALLEH
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SYAHRIZAL SALLEH
description THERE IS DISCLOSED A CIRCUIT ADAPTED TO EXHIBIT DIODE CHARACTERISTICS. THE CIRCUIT COMPRISES: A DIODE INPUT NODE (120);•A DIODE OUTPUT NODE (130);•A GATE BIAS SUB-CIRCUIT (155) HAVING A GATE BIAS NODE (170), THE GATE BIAS SUB-CIRCUIT (155) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120) AND ADAPTED TO APPLY A GATE BIAS POTENTIAL DERIVED FROM THE INPUT SIGNAL POTENTIAL APPLIED AT THE DIODE INPUT NODE (120) TO THEREBY PROVIDE A GATE BIAS POTENTIAL TO THE GATE BIAS NODE (170); AND A FIRST PMOS TRANSISTOR (140) HAVING A DRAIN TERMINAL (142) A SOURCE TERMINAL (146), A BULK TERMINAL (148) AND A GATE TERMINAL (144), THE DRAIN TERMINAL (142) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120), THE SOURCE (146) AND BULK (148) TERMINALS ELECTRICALLY CONNECTED TO THE DIODE OUTPUT NODE (130) AND THE GATE TERMINAL (144) ELECTRICALLY CONNECTED TO THE GATE BIAS NODE (170). (FIG. 1)
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_MY151147A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>MY151147A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_MY151147A3</originalsourceid><addsrcrecordid>eNrjZLAJ8PUPVggJcvQL9gwO8Q9ScPYMcg71DFFwA7JdIzw8nTxDPP3cFVw8_V1cFZw9HIMcnUNcg4BqPZ2DeRhY0xJzilN5oTQ3g5yba4izh25qQX58anFBYnJqXmpJvG-koamhoYm5ozFBBQBCNCjL</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS</title><source>esp@cenet</source><creator>SYAHRIZAL SALLEH</creator><creatorcontrib>SYAHRIZAL SALLEH</creatorcontrib><description>THERE IS DISCLOSED A CIRCUIT ADAPTED TO EXHIBIT DIODE CHARACTERISTICS. THE CIRCUIT COMPRISES: A DIODE INPUT NODE (120);•A DIODE OUTPUT NODE (130);•A GATE BIAS SUB-CIRCUIT (155) HAVING A GATE BIAS NODE (170), THE GATE BIAS SUB-CIRCUIT (155) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120) AND ADAPTED TO APPLY A GATE BIAS POTENTIAL DERIVED FROM THE INPUT SIGNAL POTENTIAL APPLIED AT THE DIODE INPUT NODE (120) TO THEREBY PROVIDE A GATE BIAS POTENTIAL TO THE GATE BIAS NODE (170); AND A FIRST PMOS TRANSISTOR (140) HAVING A DRAIN TERMINAL (142) A SOURCE TERMINAL (146), A BULK TERMINAL (148) AND A GATE TERMINAL (144), THE DRAIN TERMINAL (142) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120), THE SOURCE (146) AND BULK (148) TERMINALS ELECTRICALLY CONNECTED TO THE DIODE OUTPUT NODE (130) AND THE GATE TERMINAL (144) ELECTRICALLY CONNECTED TO THE GATE BIAS NODE (170). (FIG. 1)</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140430&amp;DB=EPODOC&amp;CC=MY&amp;NR=151147A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140430&amp;DB=EPODOC&amp;CC=MY&amp;NR=151147A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SYAHRIZAL SALLEH</creatorcontrib><title>PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS</title><description>THERE IS DISCLOSED A CIRCUIT ADAPTED TO EXHIBIT DIODE CHARACTERISTICS. THE CIRCUIT COMPRISES: A DIODE INPUT NODE (120);•A DIODE OUTPUT NODE (130);•A GATE BIAS SUB-CIRCUIT (155) HAVING A GATE BIAS NODE (170), THE GATE BIAS SUB-CIRCUIT (155) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120) AND ADAPTED TO APPLY A GATE BIAS POTENTIAL DERIVED FROM THE INPUT SIGNAL POTENTIAL APPLIED AT THE DIODE INPUT NODE (120) TO THEREBY PROVIDE A GATE BIAS POTENTIAL TO THE GATE BIAS NODE (170); AND A FIRST PMOS TRANSISTOR (140) HAVING A DRAIN TERMINAL (142) A SOURCE TERMINAL (146), A BULK TERMINAL (148) AND A GATE TERMINAL (144), THE DRAIN TERMINAL (142) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120), THE SOURCE (146) AND BULK (148) TERMINALS ELECTRICALLY CONNECTED TO THE DIODE OUTPUT NODE (130) AND THE GATE TERMINAL (144) ELECTRICALLY CONNECTED TO THE GATE BIAS NODE (170). (FIG. 1)</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAJ8PUPVggJcvQL9gwO8Q9ScPYMcg71DFFwA7JdIzw8nTxDPP3cFVw8_V1cFZw9HIMcnUNcg4BqPZ2DeRhY0xJzilN5oTQ3g5yba4izh25qQX58anFBYnJqXmpJvG-koamhoYm5ozFBBQBCNCjL</recordid><startdate>20140430</startdate><enddate>20140430</enddate><creator>SYAHRIZAL SALLEH</creator><scope>EVB</scope></search><sort><creationdate>20140430</creationdate><title>PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS</title><author>SYAHRIZAL SALLEH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_MY151147A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SYAHRIZAL SALLEH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SYAHRIZAL SALLEH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS</title><date>2014-04-30</date><risdate>2014</risdate><abstract>THERE IS DISCLOSED A CIRCUIT ADAPTED TO EXHIBIT DIODE CHARACTERISTICS. THE CIRCUIT COMPRISES: A DIODE INPUT NODE (120);•A DIODE OUTPUT NODE (130);•A GATE BIAS SUB-CIRCUIT (155) HAVING A GATE BIAS NODE (170), THE GATE BIAS SUB-CIRCUIT (155) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120) AND ADAPTED TO APPLY A GATE BIAS POTENTIAL DERIVED FROM THE INPUT SIGNAL POTENTIAL APPLIED AT THE DIODE INPUT NODE (120) TO THEREBY PROVIDE A GATE BIAS POTENTIAL TO THE GATE BIAS NODE (170); AND A FIRST PMOS TRANSISTOR (140) HAVING A DRAIN TERMINAL (142) A SOURCE TERMINAL (146), A BULK TERMINAL (148) AND A GATE TERMINAL (144), THE DRAIN TERMINAL (142) ELECTRICALLY CONNECTED TO THE DIODE INPUT NODE (120), THE SOURCE (146) AND BULK (148) TERMINALS ELECTRICALLY CONNECTED TO THE DIODE OUTPUT NODE (130) AND THE GATE TERMINAL (144) ELECTRICALLY CONNECTED TO THE GATE BIAS NODE (170). (FIG. 1)</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_MY151147A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title PMOS TRANSISTOR CIRCUIT FOR EXHIBITING DIODE CHARACTERISTICS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T04%3A53%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SYAHRIZAL%20SALLEH&rft.date=2014-04-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EMY151147A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true