BUFFER CIRCUIT

BUFFER CIRCUIT THE PRESENT INVENTION RELATES TO A BUFFER CIRCUIT (1 00), FOR EXAMPLE FOR USE IN AMPLIFYING A CARRIER SIGNAL IN AN RF COMMUNICATIONS SYSTEM BEFORE OUTPUT TO A 5 PHASE LOCK LOOP. IN BROAD TERMS, THE BUFFER CIRCUIT (1 00) INCLUDES A PAIR OF TRANSISTORS (MNI, MP2) INCLUDING ONE NMOS TRANSISTOR AND ONE PMOS TRANSISTOR COUPLED IN A DIGITAL INVERTER ARRANGEMENT. THE BUFFER CIRCUIT (100) FURTHER INCLUDES, MEANS, CONNECTED TO THE SOURCE TERMINAL OF TRANSISTOR MP2, WHICH OPERATES AS A SHORT CIRCUIT TO GROUND UPON APPLICATION OF A HIGH FREQUENCY INPUT SIGNAL; AND A 1 0 CURRENT LIMITING SUB-CIRCUIT ALSO CONNECTED TO THE SOURCE TERMINAL OF THE TRANSISTOR MP2 THAT CONTROLS THE CURRENT THROUGH THE BUFFER CIRCUIT.