COMPLIANT SURFACE LAYER FOR FLIP-CHIP ELECTRONIC PACKAGES AND METHOD FOR FORMING SAME

FLIP-CHIP ELECTRONIC PACKAGES ARE PROVIDED WITH A COMPLIANT SURFACE LAYER, NORMALLY POSITIONED BETWEEN AN UNDERFILL LAYER AND A SUBSTRATE SUCH AS A CHIP CARRIER OR A PRINTED CIRCUIT BOARD OR CARD, WHICH REDUCES STRESS AND STRAIN RESULTING FROM DIFFERENCES IN COEFFICIENTS OF THERMAL EXPANSION BETWEEN THE CHIP AND SUBSTRATE. THE COMPLIANT LAYER, WHICH SHOULD HAVE STORAGE MODULUS OF LESS THAN ½ THE MODULUS OF THE SUBSTRATE, PREFERABLY BETWEEN ABOUT 50,000 PSI AND ABOUT 20,000 PSI, MAY COMPRISE RUBBERY MATERIALS SUCH AS SILICONE, VIRCO-PLASTIC POLYMERS SUCH AS POLYTETRAFLUOROETHYLENE OR INTERPENETRATING POLYMER NETWORKS (IPNS). PHOTOSENSITIVE IPNS USED FOR SOLDER MARKS ARE PREFERRED.