BOUNDARY SCAN METHOD FOR TERMINATING OR MODIFYING INTEGRATED CIRCUIT OPERATING MODES

A JTAG BOUNDRY SCAN METHOD BY WHICH THE ON-CHIP SYSTEM LOGIC (OCSL) OF AN INTEGRATED CIRCUIT IS CHANGED BY USE OF A STATE MACHINE WHICH, AMONG OTHER FUNCTIONS, ALLOWS A PREDEFINED SET OF INSTRUCTIONS TO BE LOADED INTO AN INSTRUCTION REGISTER AND THEN EXECUTED. THE PREDEFINED INSTRUCTIONS ARE DESIGNE...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	SRINIVAS RAMAMURTHY, EUGENE JINGLUM TAM, GEOFFREY S. GONGWER, JAMES FAHEY, JR
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A JTAG BOUNDRY SCAN METHOD BY WHICH THE ON-CHIP SYSTEM LOGIC (OCSL) OF AN INTEGRATED CIRCUIT IS CHANGED BY USE OF A STATE MACHINE WHICH, AMONG OTHER FUNCTIONS, ALLOWS A PREDEFINED SET OF INSTRUCTIONS TO BE LOADED INTO AN INSTRUCTION REGISTER AND THEN EXECUTED. THE PREDEFINED INSTRUCTIONS ARE DESIGNED TO FOLLOW IN SEQUENCE AFTER CERTAIN OTHER PREVIOUS INSTRUCTIONS. THE INSTRUCTIONS CHANGE THE OCSL FROM ONE STATE TO ANOTHER STATE AND ALLOWS THE STATE TO BE CHANGED WITHOUT THE NEED OF A FULL DEVICE RESET. ADDITIONAL INSTRUCTIONS WITHIN THIS INVENTION WERE CREATED TO HAVE ATTENDANT OPERATING MODES FOR WHICH TERMINATION IS SELF TIMED WITHIN THE INTEGRATED CIRCUIT. ADDITIONAL INSTRUCTIONS FURTHER CONTROL THE IMPLEMENTATION OF THE INSTRUCTION EXECUTION WITHIN THE STATE MACHINE.(FIG 5)