SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, SEMICONDUCTOR MODULE AND A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICES, SEMICONDUCTOR WAFERS, AND REMICONDUCTOR MODULES ARE PROVIDED: WHEREIN THE SEMICONDUCTOR DEVICE HAS A SMALL WARP; DAMAGES AT CHIP EDGE AND CRACKS IN A DROPPING TEST ARE SCARCELY GENERATED; AND THE SEMICONDUCTOR DEVICE IS SUPERIOR IN MOUNTING RELIABILITY AND MASS PRODUCIBILITY....

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Hauptverfasser: SYUJI EGUCHI, TOSHIYA SATOH, HIROYOSHI KOKAKU, MASANORI SEGAWA, NOBUTAKE TSUYUNO, ICHIRO ANJOH, ASAO NISHIMURA, TOSHIAKI ISHII, TAKUMI UENO, MASAHIKO OGINO, AKIRA NAGAI
Format: Patent
Sprache:eng
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Zusammenfassung:SEMICONDUCTOR DEVICES, SEMICONDUCTOR WAFERS, AND REMICONDUCTOR MODULES ARE PROVIDED: WHEREIN THE SEMICONDUCTOR DEVICE HAS A SMALL WARP; DAMAGES AT CHIP EDGE AND CRACKS IN A DROPPING TEST ARE SCARCELY GENERATED; AND THE SEMICONDUCTOR DEVICE IS SUPERIOR IN MOUNTING RELIABILITY AND MASS PRODUCIBILITY. THE SEMICONDUCTOR DEVICE 17 COMPRISING: A SEMICONDUCTOR CHIP 64; A POROUS STRESS RELAXING LAYER 3 PROVIDED ON THE PLANE, WHEREON CIRCUITS AND ELECTRODES ARE FORMED, OF THE SEMICONDUCTOR CHIP; A CIRCUIT LAYER 2 PROVIDED ON THE STRESS RELAXING LAYER AND CONNECTED TO THE ELECTRODES; AND EXTERNAL TERMINALS 10 PROVIDED ON THE CIRCUIT LAYER; WHEREIN AN ORGANIC PROTECTING FILM 7 IS FORMED ON THE PLANE, OPPOSITE TO THE STRESS RELAXING LAYER, OF THE SEMICONDUCTOR CHIP, AND RESPECTIVE SIDE PLANES OF. THE STRESS RELAXING LAYER, THE SEMICONDUCTOR CHIP 6, AND THE PROTECTING FILM 7 ARE EXPOSED OUTSIDE ON A SAME PLANE.(FIG. 1)