INTEGRATED MANUFACTURING PACKAGING PROCESS

A PROCESS OF FABRICATING A CIRCUITIZED SUBSTRATE IS PROVIDED WHICH COMPRISING THE STEPS OF: PROVIDING AN ORGANIC SUBSTRATE (12) HAVING CIRCUITRY (14) THEREON; APPLYING A DIELECTRONIC FILM (16, 30) ON THE ORGANIC SUBSTRATE; FORMING MICROVIAS (18) IN SAID DIELECTRIC FILM; SPUTTERING A METAL SEED LAYER...

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Bibliographische Detailangaben
Hauptverfasser:	VOYA RISTA MARKOVICH, JAMES WARREN WILSON, GERARD WALTER JONES, WILLIAM JOHN RUDIK, ROSS WILLIAM KEESLER, WILLIAM EARL WILSON
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC INCANDESCENT LAMPS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Beschreibung
Zusammenfassung:	A PROCESS OF FABRICATING A CIRCUITIZED SUBSTRATE IS PROVIDED WHICH COMPRISING THE STEPS OF: PROVIDING AN ORGANIC SUBSTRATE (12) HAVING CIRCUITRY (14) THEREON; APPLYING A DIELECTRONIC FILM (16, 30) ON THE ORGANIC SUBSTRATE; FORMING MICROVIAS (18) IN SAID DIELECTRIC FILM; SPUTTERING A METAL SEED LAYER (20) ON THE DIELECTRIC FILM AND IN SAID MICROVIAS; PLATING A METALLIC LAYER (22) ON THE METAL SEED LAYER; AND FORMING A CIRCUIT PATTERN THEREON.(FIGURE 1 (E))