TIMING VERIFICATION CIRCUIT

Disclosed is a timing check circuit comprising a signal change detector, connected to a first input terminal, a decision window generator for receiving the output of the signal change detector, a decision condition detector, connected to a second input terminal, and an AND gate for obtaining a logical product of the output of the decision window generator and the output of the decision condition detector. The output of this AND gate is connected to a clock input terminal of a flip-flop of a logic cell in a specific system. When there is an output from the AND gate, it is determined that an error has occurred. With this structure, a timing check system designed on the premise that logic cells in a specific system are used can execute timing check for a functional macro constituted of a combination of logic cells in the specific system.