A SEMICONDUCTOR MEMORY DEVICE INCLUDING AN APPARATUS FOR REDUCING LOAD OF DATA BUS LINE

A memory device reduces a load of a data bus line, and increases a data transmission speed. The memory device includes: a data bus line which performs a data input/output operation a plurality of memory blocks(2001-2064), and is divided into two data bus lines; and a data bus line load reduction apparatus(2400) which selects a data bus line performing I/O operation of a memory block's data selected by a memory block address among the memory blocks(2001-2064) between two data bus lines according to a data bus line control signal(PSOLZL, PSOLZR). Also, the data bus line load reduction apparatus(2400) minimizes another data bus line load not selected.