DIGITAL PHASE SYNCHRONIZING LOOP CIRCUIT & METHOD

The circuit which is simple to implement and minimizes the effect of noise, is composed of a fully digital circuit for the digital communication systems. The circuit includes: (a) an edge detector which detects edge from the input data; (b) a clock generator which generates synchronized clock signal with the input data by using a detected edge data. The edge detector contains a delay unit which delays the input data for a half clock cycle, an XOR gate, and a latch for synchronizing the input data with the clock generator output.