PLANERIZING METHOD OF INTER METAL LAYER FOR SEMICONDUCTOR DEVICE
(A) forming a metal layer for inhibiting it from etching, mediating metal, and a metal mask layer (4) sequentially after the formation of a buried metal (1) on the fixed area of the substrate, (B) spreading a photoresist film and patterning photoresist film (5) on the buried metal, (C) 1st etching t...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng ; kor |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | JONG, YANG - HUI |
| description | (A) forming a metal layer for inhibiting it from etching, mediating metal, and a metal mask layer (4) sequentially after the formation of a buried metal (1) on the fixed area of the substrate, (B) spreading a photoresist film and patterning photoresist film (5) on the buried metal, (C) 1st etching the mask layer of mediating metal (4) and mediating metal (3) by using the patterned photoresist film and removing photoresist film, (D) evaporating a photoresist film on the whole surface and forming a micro-pattern on the top of the mediating buried metal (1) and removing exposed metal layer (2) for inhibiting it from etching, (E) forming an insulating layer (7) on the whole area, spreading photoresist film (8) over the insulating layer, and leveling the insulating layer (7), (F) removing the mask layer (4), and (G) evaporating the 2nd metal (9) on the whole surface of resulting material and patterning it for connection with mediating material. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR940000154BB1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR940000154BB1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR940000154BB13</originalsourceid><addsrcrecordid>eNrjZHAI8HH0cw3yjPL0c1fwdQ3x8HdR8HdT8PQLcQ0C8R19FHwcI4FsN_8ghWBXX09nfz-XUOcQIM_FNczT2ZWHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsR7B1maGACBoamJk5OhMXGqAFkLK5o</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PLANERIZING METHOD OF INTER METAL LAYER FOR SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>JONG, YANG - HUI</creator><creatorcontrib>JONG, YANG - HUI</creatorcontrib><description>(A) forming a metal layer for inhibiting it from etching, mediating metal, and a metal mask layer (4) sequentially after the formation of a buried metal (1) on the fixed area of the substrate, (B) spreading a photoresist film and patterning photoresist film (5) on the buried metal, (C) 1st etching the mask layer of mediating metal (4) and mediating metal (3) by using the patterned photoresist film and removing photoresist film, (D) evaporating a photoresist film on the whole surface and forming a micro-pattern on the top of the mediating buried metal (1) and removing exposed metal layer (2) for inhibiting it from etching, (E) forming an insulating layer (7) on the whole area, spreading photoresist film (8) over the insulating layer, and leveling the insulating layer (7), (F) removing the mask layer (4), and (G) evaporating the 2nd metal (9) on the whole surface of resulting material and patterning it for connection with mediating material.</description><edition>5</edition><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940107&DB=EPODOC&CC=KR&NR=940000154B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940107&DB=EPODOC&CC=KR&NR=940000154B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JONG, YANG - HUI</creatorcontrib><title>PLANERIZING METHOD OF INTER METAL LAYER FOR SEMICONDUCTOR DEVICE</title><description>(A) forming a metal layer for inhibiting it from etching, mediating metal, and a metal mask layer (4) sequentially after the formation of a buried metal (1) on the fixed area of the substrate, (B) spreading a photoresist film and patterning photoresist film (5) on the buried metal, (C) 1st etching the mask layer of mediating metal (4) and mediating metal (3) by using the patterned photoresist film and removing photoresist film, (D) evaporating a photoresist film on the whole surface and forming a micro-pattern on the top of the mediating buried metal (1) and removing exposed metal layer (2) for inhibiting it from etching, (E) forming an insulating layer (7) on the whole area, spreading photoresist film (8) over the insulating layer, and leveling the insulating layer (7), (F) removing the mask layer (4), and (G) evaporating the 2nd metal (9) on the whole surface of resulting material and patterning it for connection with mediating material.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAI8HH0cw3yjPL0c1fwdQ3x8HdR8HdT8PQLcQ0C8R19FHwcI4FsN_8ghWBXX09nfz-XUOcQIM_FNczT2ZWHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsR7B1maGACBoamJk5OhMXGqAFkLK5o</recordid><startdate>19940107</startdate><enddate>19940107</enddate><creator>JONG, YANG - HUI</creator><scope>EVB</scope></search><sort><creationdate>19940107</creationdate><title>PLANERIZING METHOD OF INTER METAL LAYER FOR SEMICONDUCTOR DEVICE</title><author>JONG, YANG - HUI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR940000154BB13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>1994</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JONG, YANG - HUI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JONG, YANG - HUI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PLANERIZING METHOD OF INTER METAL LAYER FOR SEMICONDUCTOR DEVICE</title><date>1994-01-07</date><risdate>1994</risdate><abstract>(A) forming a metal layer for inhibiting it from etching, mediating metal, and a metal mask layer (4) sequentially after the formation of a buried metal (1) on the fixed area of the substrate, (B) spreading a photoresist film and patterning photoresist film (5) on the buried metal, (C) 1st etching the mask layer of mediating metal (4) and mediating metal (3) by using the patterned photoresist film and removing photoresist film, (D) evaporating a photoresist film on the whole surface and forming a micro-pattern on the top of the mediating buried metal (1) and removing exposed metal layer (2) for inhibiting it from etching, (E) forming an insulating layer (7) on the whole area, spreading photoresist film (8) over the insulating layer, and leveling the insulating layer (7), (F) removing the mask layer (4), and (G) evaporating the 2nd metal (9) on the whole surface of resulting material and patterning it for connection with mediating material.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; kor |
| recordid | cdi_epo_espacenet_KR940000154BB1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | PLANERIZING METHOD OF INTER METAL LAYER FOR SEMICONDUCTOR DEVICE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T11%3A48%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JONG,%20YANG%20-%20HUI&rft.date=1994-01-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR940000154BB1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |