TRI-STATE OUTPUT CIRCUIT OF BICMOS

TRI-STATE OUTPUT CIRCUIT OF BICMOS

The circuit having low power consumption and strong driving charactristic comprises PMOS and NMOS transistors (M1,M2,M3) having gates connected to an input node (Data in), NMOS transistors (M6,M8,M9) having gates to be applied with tristate control signal, a PMOS transistor (M5) having a gate to be...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HYON, JIN - IL, KIM, YONG - MIN, YU, HA - YONG, SONG, WON - CHOL
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:The circuit having low power consumption and strong driving charactristic comprises PMOS and NMOS transistors (M1,M2,M3) having gates connected to an input node (Data in), NMOS transistors (M6,M8,M9) having gates to be applied with tristate control signal, a PMOS transistor (M5) having a gate to be applied with tristate control signal and having a drain connected to a driving voltage source, an NMOS transistor (M7) having a gate connected to the TR (M5) source and TR (M6) drain, and a drain connected to the TR (M3) source, an NMOS transistor (M4) connected to the TR's (M7,M1,M8), an NPN transistor (Q1) connected to the TR's (M1,M3), the driving voltage source (VDD) and an output node (Data out), an NPN transistor (Q2) connected to the TR's (M7,M9), and output node, and a capacitor (C1) connected between the output node and a ground.