MEMORY DEVICE CONSIST OF 3 TRANSISTORS USING I BIT LINE AND/WORD LINE

In the memory cell comprising the three transistor by using one bit line and one word line, a capacitor (C1) terminal is connected to a gate of MOS transistor (M1) and also to a source of MOS transistor (M3). The another terminal of capacitor (C1) and a source of M1 are connected to the substrate bias. The drain of M1 is connected to the source of M2. The drain of M2 and M3 is connected to the bit line, and the gate of M2 and M3 is connected to the word line. The threshold voltage of M3 is set higher than that of M2. The electric potential of word line is higher than the threshold voltage of M3 in the case of reading of information.