P-N PROTECTION DEVICE WITH P-N JUNCTION DEVICES MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY

P-N PROTECTION DEVICE WITH P-N JUNCTION DEVICES MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY

반도체 디바이스는, 상부 표면을 포함하는 반도체 바디, 반도체 바디의 상부 표면 상에 배치된 입력 단자 및 출력 단자, 반도체 바디에 모놀리식으로 통합된 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스, 및 입력 단자와 출력 단자 사이에 연결되고 저역 통과 필터 및 전압 클램핑 디바이스를 포함하는 신호 라인 보호 회로를 포함하고, 저역 통과 필터 및 전압 클램핑 디바이스 각각은 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스를 포함한다. A semiconductor device includes a semicondu...

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Hauptverfasser: LAURER JULIANE, WERTHMANN HUBERT, SCHAFFER JOSEF PAUL
Format: Patent
Sprache:eng ; kor
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator LAURER JULIANE
WERTHMANN HUBERT
SCHAFFER JOSEF PAUL
description 반도체 디바이스는, 상부 표면을 포함하는 반도체 바디, 반도체 바디의 상부 표면 상에 배치된 입력 단자 및 출력 단자, 반도체 바디에 모놀리식으로 통합된 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스, 및 입력 단자와 출력 단자 사이에 연결되고 저역 통과 필터 및 전압 클램핑 디바이스를 포함하는 신호 라인 보호 회로를 포함하고, 저역 통과 필터 및 전압 클램핑 디바이스 각각은 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스를 포함한다. A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.
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A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240206&amp;DB=EPODOC&amp;CC=KR&amp;NR=20240016915A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25546,76297</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240206&amp;DB=EPODOC&amp;CC=KR&amp;NR=20240016915A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LAURER JULIANE</creatorcontrib><creatorcontrib>WERTHMANN HUBERT</creatorcontrib><creatorcontrib>SCHAFFER JOSEF PAUL</creatorcontrib><title>P-N PROTECTION DEVICE WITH P-N JUNCTION DEVICES MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY</title><description>반도체 디바이스는, 상부 표면을 포함하는 반도체 바디, 반도체 바디의 상부 표면 상에 배치된 입력 단자 및 출력 단자, 반도체 바디에 모놀리식으로 통합된 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스, 및 입력 단자와 출력 단자 사이에 연결되고 저역 통과 필터 및 전압 클램핑 디바이스를 포함하는 신호 라인 보호 회로를 포함하고, 저역 통과 필터 및 전압 클램핑 디바이스 각각은 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스를 포함한다. A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEgM0PVTCAjyD3F1DvH091NwcQ3zdHZVCPcM8VAASXmF-iFLBCv4-vv5-wBlPZ0dfXwiFTz9QlzdgxxDXF2ATAVHhWBXX09nfz-XUOcQ_yAFJ3-XSB4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEu8dZGRgZGJgYGhmaWjqaEycKgB7GDSK</recordid><startdate>20240206</startdate><enddate>20240206</enddate><creator>LAURER JULIANE</creator><creator>WERTHMANN HUBERT</creator><creator>SCHAFFER JOSEF PAUL</creator><scope>EVB</scope></search><sort><creationdate>20240206</creationdate><title>P-N PROTECTION DEVICE WITH P-N JUNCTION DEVICES MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY</title><author>LAURER JULIANE ; WERTHMANN HUBERT ; SCHAFFER JOSEF PAUL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20240016915A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LAURER JULIANE</creatorcontrib><creatorcontrib>WERTHMANN HUBERT</creatorcontrib><creatorcontrib>SCHAFFER JOSEF PAUL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LAURER JULIANE</au><au>WERTHMANN HUBERT</au><au>SCHAFFER JOSEF PAUL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>P-N PROTECTION DEVICE WITH P-N JUNCTION DEVICES MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY</title><date>2024-02-06</date><risdate>2024</risdate><abstract>반도체 디바이스는, 상부 표면을 포함하는 반도체 바디, 반도체 바디의 상부 표면 상에 배치된 입력 단자 및 출력 단자, 반도체 바디에 모놀리식으로 통합된 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스, 및 입력 단자와 출력 단자 사이에 연결되고 저역 통과 필터 및 전압 클램핑 디바이스를 포함하는 신호 라인 보호 회로를 포함하고, 저역 통과 필터 및 전압 클램핑 디바이스 각각은 제1 p-n 접합 디바이스 및 제2 p-n 접합 디바이스를 포함한다. A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title P-N PROTECTION DEVICE WITH P-N JUNCTION DEVICES MONOLITHICALLY INTEGRATED IN A SEMICONDUCTOR BODY
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