Method for fabricating a semiconductor package

반도체 패키지가 제공된다. 반도체 패키지는 하면에 솔더볼이 형성된 반도체 칩을 제공하고, 반도체 칩의 상면 상에 접착층을 형성하고, 솔더볼을 이용하여 제1 웨이퍼 상에 반도체 칩을 실장시키고, 제1 웨이퍼 및 반도체 칩 상에서, 접착층에 제2 웨이퍼를 본딩시키고, 제1 웨이퍼와 제2 웨이퍼 사이에 몰딩층을 형성하고, 및 제1 웨이퍼, 몰딩층 및 제2 웨이퍼를 절단하는 것을 포함한다. A method of fabricating a semiconductor package includes providing a semiconductor c...

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Hauptverfasser: LEE JEONG HYUN, PARK JI YONG, YIM CHOONG BIN
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Sprache:eng ; kor
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PARK JI YONG
YIM CHOONG BIN
description 반도체 패키지가 제공된다. 반도체 패키지는 하면에 솔더볼이 형성된 반도체 칩을 제공하고, 반도체 칩의 상면 상에 접착층을 형성하고, 솔더볼을 이용하여 제1 웨이퍼 상에 반도체 칩을 실장시키고, 제1 웨이퍼 및 반도체 칩 상에서, 접착층에 제2 웨이퍼를 본딩시키고, 제1 웨이퍼와 제2 웨이퍼 사이에 몰딩층을 형성하고, 및 제1 웨이퍼, 몰딩층 및 제2 웨이퍼를 절단하는 것을 포함한다. A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20240012041A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20240012041A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20240012041A3</originalsourceid><addsrcrecordid>eNrjZNDzTS3JyE9RSMsvUkhLTCrKTE4sycxLV0hUKE7NzUzOz0spTS4ByhUkJmcnpqfyMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjUYqCq1LzUknjvICMDIxMDA0MjAxNDR2PiVAEAmAcrPw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for fabricating a semiconductor package</title><source>esp@cenet</source><creator>LEE JEONG HYUN ; PARK JI YONG ; YIM CHOONG BIN</creator><creatorcontrib>LEE JEONG HYUN ; PARK JI YONG ; YIM CHOONG BIN</creatorcontrib><description>반도체 패키지가 제공된다. 반도체 패키지는 하면에 솔더볼이 형성된 반도체 칩을 제공하고, 반도체 칩의 상면 상에 접착층을 형성하고, 솔더볼을 이용하여 제1 웨이퍼 상에 반도체 칩을 실장시키고, 제1 웨이퍼 및 반도체 칩 상에서, 접착층에 제2 웨이퍼를 본딩시키고, 제1 웨이퍼와 제2 웨이퍼 사이에 몰딩층을 형성하고, 및 제1 웨이퍼, 몰딩층 및 제2 웨이퍼를 절단하는 것을 포함한다. A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240129&amp;DB=EPODOC&amp;CC=KR&amp;NR=20240012041A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240129&amp;DB=EPODOC&amp;CC=KR&amp;NR=20240012041A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE JEONG HYUN</creatorcontrib><creatorcontrib>PARK JI YONG</creatorcontrib><creatorcontrib>YIM CHOONG BIN</creatorcontrib><title>Method for fabricating a semiconductor package</title><description>반도체 패키지가 제공된다. 반도체 패키지는 하면에 솔더볼이 형성된 반도체 칩을 제공하고, 반도체 칩의 상면 상에 접착층을 형성하고, 솔더볼을 이용하여 제1 웨이퍼 상에 반도체 칩을 실장시키고, 제1 웨이퍼 및 반도체 칩 상에서, 접착층에 제2 웨이퍼를 본딩시키고, 제1 웨이퍼와 제2 웨이퍼 사이에 몰딩층을 형성하고, 및 제1 웨이퍼, 몰딩층 및 제2 웨이퍼를 절단하는 것을 포함한다. A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzTS3JyE9RSMsvUkhLTCrKTE4sycxLV0hUKE7NzUzOz0spTS4ByhUkJmcnpqfyMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjUYqCq1LzUknjvICMDIxMDA0MjAxNDR2PiVAEAmAcrPw</recordid><startdate>20240129</startdate><enddate>20240129</enddate><creator>LEE JEONG HYUN</creator><creator>PARK JI YONG</creator><creator>YIM CHOONG BIN</creator><scope>EVB</scope></search><sort><creationdate>20240129</creationdate><title>Method for fabricating a semiconductor package</title><author>LEE JEONG HYUN ; PARK JI YONG ; YIM CHOONG BIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20240012041A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE JEONG HYUN</creatorcontrib><creatorcontrib>PARK JI YONG</creatorcontrib><creatorcontrib>YIM CHOONG BIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE JEONG HYUN</au><au>PARK JI YONG</au><au>YIM CHOONG BIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for fabricating a semiconductor package</title><date>2024-01-29</date><risdate>2024</risdate><abstract>반도체 패키지가 제공된다. 반도체 패키지는 하면에 솔더볼이 형성된 반도체 칩을 제공하고, 반도체 칩의 상면 상에 접착층을 형성하고, 솔더볼을 이용하여 제1 웨이퍼 상에 반도체 칩을 실장시키고, 제1 웨이퍼 및 반도체 칩 상에서, 접착층에 제2 웨이퍼를 본딩시키고, 제1 웨이퍼와 제2 웨이퍼 사이에 몰딩층을 형성하고, 및 제1 웨이퍼, 몰딩층 및 제2 웨이퍼를 절단하는 것을 포함한다. A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method for fabricating a semiconductor package
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