INTEGRATED CIRCUIT DEVICES INCLUDING METAL LINES SPACED APART FROM METAL VIAS AND RELATED FABRICATION METHODS

INTEGRATED CIRCUIT DEVICES INCLUDING METAL LINES SPACED APART FROM METAL VIAS AND RELATED FABRICATION METHODS

Provided are integrated circuit devices. The integrated circuit device includes a first insulating layer and a metal via that is in the first insulating layer. The integrated circuit device includes a second insulating layer on the first insulating layer. The integrated circuit device includes a con...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HONG WON HYUK, LEE JANG GEUN, CHOI JAE MYUNG, SEO KANG ILL
Format: Patent
Sprache:eng ; kor
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Provided are integrated circuit devices. The integrated circuit device includes a first insulating layer and a metal via that is in the first insulating layer. The integrated circuit device includes a second insulating layer on the first insulating layer. The integrated circuit device includes a conductive material that is between sidewalls of the second insulating layer and on the metal via. Moreover, the integrated circuit device includes a metal line that is on the conductive material and/or the second insulating layer. In addition, related methods for forming integrated circuit devices are also provided. 집적회로 소자가 제공된다. 집적회로 소자는 제1 절연층 및 제1 절연층 내에 있는 금속 비아를 포함한다. 집적회로 소자는 제1 절연층 상에 있는 제2 절연층을 포함한다. 집적회로 소자는 제2 절연층의 측벽들 및 금속 비아 상 사이에 있는 전도성 재료를 포함한다. 또한, 집적회로 소자는 전도성 재료 및/또는 제2 절연층 위에 있는 금속 라인을 포함한다. 또한, 집적회로 소자들을 형성하는 관련된 방법들이 제공된다.