SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

The present invention provides a semiconductor device which includes no reinforcing fiber such as glass cross, nonwoven fabric, or the like in an insulating material layer, and enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in int...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: TAMAKAWA MICHIAKI, IWASAKI TOSHIHIRO, ISHIDO KIMINORI
Format: Patent
Sprache:eng ; kor
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The present invention provides a semiconductor device which includes no reinforcing fiber such as glass cross, nonwoven fabric, or the like in an insulating material layer, and enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. Provided is the semiconductor device comprising: insulation material layers (101, 108) which include one or more semiconductor elements (107a, 107b) sealed by an insulation material (114b) not including a reinforcement fiber, a plurality of metal thin film wiring layers (102), and a metal via (109) electrically connecting the metal thin film wiring layers to each other and connecting an electrode (106) of the semiconductor element to the metal thin film wiring layer (102); and a bending adjustment layer (123) which is disposed on one main surface side of the insulation material layers, and offsets bending of the insulation material layers (101, 108) to reduce bending of the semiconductor device. 본 발명은 절연 재료층에 글래스 크로스나 부직포 등의 보강섬유를 포함하지 않는, 금속 박막 배선층의 정밀화, 금속 비어의 소경화, 및 층간 두께의 박형화를 가능하게 하는 반도체장치를 제공하는 것. 보강섬유를 포함하지 않는 절연재료(114b)에 의해서 밀봉된 1개 내지 복수의 반도체 소자(107a, 107b)와, 복수의 금속 박막 배선층(102)과, 상기 금속 박막 배선층간, 및, 상기 반도체 소자의 전극(106)과 금속 박막 배선층(102)을 전기적으로 접속하는 금속 비어(109)를 포함하는 절연 재료층(101, 108)과, 상기 절연 재료층의 한쪽의 주면측에 배치되고, 상기 절연 재료층(101, 108)의 휨을 상쇄하여, 반도체장치의 휨을 저감하는 휨 조정층(123)을 구비하는 반도체장치를 제공하는 것이다.