1 one-bit full adder
The present invention relates to a one-bit full adder. The disclosed one-bit full adder may include: a first operation unit which includes a first input part configured to receive a carry-in signal and a first exclusive NOR (XNOR) operation part serially connected to the first input part; and a seco...
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| creator | PARK SU GIL RA CHANG HO KIM HYUN GYEONG JEON JONG WOOK |
| description | The present invention relates to a one-bit full adder. The disclosed one-bit full adder may include: a first operation unit which includes a first input part configured to receive a carry-in signal and a first exclusive NOR (XNOR) operation part serially connected to the first input part; and a second operation unit which includes a second input part configured to receive an inverted signal of the carry-in signal and a second XNOR operation part serially connected to the second input part. Here, the first and second operation units are connected in parallel through a first bit line, to which an addition output signal of the one-bit full adder is provided, and each of the first and second XNOR operation parts includes a plurality of ferroelectric field effect transistor (FeFET) elements. Therefore, the one-bit full adder can be realized with a reduced number of elements.
1 비트 전가산기(full adder)가 개시된다. 개시된 1 비트 전가산기는, 캐리입력(carry-in) 신호를 입력받도록 구성된 제1 입력부 및 상기 제1 입력부에 직렬 접속된 제1 XNOR(exclusive NOR) 연산부를 포함하는 제1 연산부, 및 상기 캐리입력 신호의 반전 신호(inverted signal)를 입력받도록 구성된 제2 입력부 및 상기 제2 입력부에 직렬 접속된 제2 XNOR 연산부를 포함하는 제2 연산부를 포함할 수 있다. 여기서 상기 제1 연산부 및 상기 제2 연산부는 상기 1 비트 전가산기의 가산출력 신호가 제공되는 제1 비트 라인을 통해 병렬 접속되고, 상기 제1 XNOR 연산부 및 상기 제2 XNOR 연산부의 각각은 두 개의 FeFET(Ferroelectric Field Effect Transistor) 소자를 포함하여 구성될 수 있다. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20230115095A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20230115095A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20230115095A3</originalsourceid><addsrcrecordid>eNrjZBAxVMjPS9VNyixRSCvNyVFITElJLeJhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGRsYGhoamBpamjsbEqQIAdN8gwQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>1 one-bit full adder</title><source>esp@cenet</source><creator>PARK SU GIL ; RA CHANG HO ; KIM HYUN GYEONG ; JEON JONG WOOK</creator><creatorcontrib>PARK SU GIL ; RA CHANG HO ; KIM HYUN GYEONG ; JEON JONG WOOK</creatorcontrib><description>The present invention relates to a one-bit full adder. The disclosed one-bit full adder may include: a first operation unit which includes a first input part configured to receive a carry-in signal and a first exclusive NOR (XNOR) operation part serially connected to the first input part; and a second operation unit which includes a second input part configured to receive an inverted signal of the carry-in signal and a second XNOR operation part serially connected to the second input part. Here, the first and second operation units are connected in parallel through a first bit line, to which an addition output signal of the one-bit full adder is provided, and each of the first and second XNOR operation parts includes a plurality of ferroelectric field effect transistor (FeFET) elements. Therefore, the one-bit full adder can be realized with a reduced number of elements.
1 비트 전가산기(full adder)가 개시된다. 개시된 1 비트 전가산기는, 캐리입력(carry-in) 신호를 입력받도록 구성된 제1 입력부 및 상기 제1 입력부에 직렬 접속된 제1 XNOR(exclusive NOR) 연산부를 포함하는 제1 연산부, 및 상기 캐리입력 신호의 반전 신호(inverted signal)를 입력받도록 구성된 제2 입력부 및 상기 제2 입력부에 직렬 접속된 제2 XNOR 연산부를 포함하는 제2 연산부를 포함할 수 있다. 여기서 상기 제1 연산부 및 상기 제2 연산부는 상기 1 비트 전가산기의 가산출력 신호가 제공되는 제1 비트 라인을 통해 병렬 접속되고, 상기 제1 XNOR 연산부 및 상기 제2 XNOR 연산부의 각각은 두 개의 FeFET(Ferroelectric Field Effect Transistor) 소자를 포함하여 구성될 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230802&DB=EPODOC&CC=KR&NR=20230115095A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230802&DB=EPODOC&CC=KR&NR=20230115095A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARK SU GIL</creatorcontrib><creatorcontrib>RA CHANG HO</creatorcontrib><creatorcontrib>KIM HYUN GYEONG</creatorcontrib><creatorcontrib>JEON JONG WOOK</creatorcontrib><title>1 one-bit full adder</title><description>The present invention relates to a one-bit full adder. The disclosed one-bit full adder may include: a first operation unit which includes a first input part configured to receive a carry-in signal and a first exclusive NOR (XNOR) operation part serially connected to the first input part; and a second operation unit which includes a second input part configured to receive an inverted signal of the carry-in signal and a second XNOR operation part serially connected to the second input part. Here, the first and second operation units are connected in parallel through a first bit line, to which an addition output signal of the one-bit full adder is provided, and each of the first and second XNOR operation parts includes a plurality of ferroelectric field effect transistor (FeFET) elements. Therefore, the one-bit full adder can be realized with a reduced number of elements.
1 비트 전가산기(full adder)가 개시된다. 개시된 1 비트 전가산기는, 캐리입력(carry-in) 신호를 입력받도록 구성된 제1 입력부 및 상기 제1 입력부에 직렬 접속된 제1 XNOR(exclusive NOR) 연산부를 포함하는 제1 연산부, 및 상기 캐리입력 신호의 반전 신호(inverted signal)를 입력받도록 구성된 제2 입력부 및 상기 제2 입력부에 직렬 접속된 제2 XNOR 연산부를 포함하는 제2 연산부를 포함할 수 있다. 여기서 상기 제1 연산부 및 상기 제2 연산부는 상기 1 비트 전가산기의 가산출력 신호가 제공되는 제1 비트 라인을 통해 병렬 접속되고, 상기 제1 XNOR 연산부 및 상기 제2 XNOR 연산부의 각각은 두 개의 FeFET(Ferroelectric Field Effect Transistor) 소자를 포함하여 구성될 수 있다.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAxVMjPS9VNyixRSCvNyVFITElJLeJhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGRsYGhoamBpamjsbEqQIAdN8gwQ</recordid><startdate>20230802</startdate><enddate>20230802</enddate><creator>PARK SU GIL</creator><creator>RA CHANG HO</creator><creator>KIM HYUN GYEONG</creator><creator>JEON JONG WOOK</creator><scope>EVB</scope></search><sort><creationdate>20230802</creationdate><title>1 one-bit full adder</title><author>PARK SU GIL ; RA CHANG HO ; KIM HYUN GYEONG ; JEON JONG WOOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20230115095A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2023</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>PARK SU GIL</creatorcontrib><creatorcontrib>RA CHANG HO</creatorcontrib><creatorcontrib>KIM HYUN GYEONG</creatorcontrib><creatorcontrib>JEON JONG WOOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARK SU GIL</au><au>RA CHANG HO</au><au>KIM HYUN GYEONG</au><au>JEON JONG WOOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>1 one-bit full adder</title><date>2023-08-02</date><risdate>2023</risdate><abstract>The present invention relates to a one-bit full adder. The disclosed one-bit full adder may include: a first operation unit which includes a first input part configured to receive a carry-in signal and a first exclusive NOR (XNOR) operation part serially connected to the first input part; and a second operation unit which includes a second input part configured to receive an inverted signal of the carry-in signal and a second XNOR operation part serially connected to the second input part. Here, the first and second operation units are connected in parallel through a first bit line, to which an addition output signal of the one-bit full adder is provided, and each of the first and second XNOR operation parts includes a plurality of ferroelectric field effect transistor (FeFET) elements. Therefore, the one-bit full adder can be realized with a reduced number of elements.
1 비트 전가산기(full adder)가 개시된다. 개시된 1 비트 전가산기는, 캐리입력(carry-in) 신호를 입력받도록 구성된 제1 입력부 및 상기 제1 입력부에 직렬 접속된 제1 XNOR(exclusive NOR) 연산부를 포함하는 제1 연산부, 및 상기 캐리입력 신호의 반전 신호(inverted signal)를 입력받도록 구성된 제2 입력부 및 상기 제2 입력부에 직렬 접속된 제2 XNOR 연산부를 포함하는 제2 연산부를 포함할 수 있다. 여기서 상기 제1 연산부 및 상기 제2 연산부는 상기 1 비트 전가산기의 가산출력 신호가 제공되는 제1 비트 라인을 통해 병렬 접속되고, 상기 제1 XNOR 연산부 및 상기 제2 XNOR 연산부의 각각은 두 개의 FeFET(Ferroelectric Field Effect Transistor) 소자를 포함하여 구성될 수 있다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE |
| title | 1 one-bit full adder |
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