MEMORY DEVICE AND OPERATION METHOD THEREOF

A memory device according to the present invention comprises: a memory block which is connected with a plurality of wordlines; a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines; and an address decoding circuit configured to connect t...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	JUNG BONG KIL, NAM SANG WAN, KIM HYUNGGON, HWANG JUSEONG, HONG YOUNHO
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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