NEUROMORPHIC MEMORY CIRCUIT AND OPERATING METHOD THEROF
A neuromorphic memory circuit according to one embodiment comprises a plurality of memory cells, wherein each of the plurality of memory cells may generate an output signal in response to the delayed input signal through a first switching element whose critical switching time varies according to a v...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | A neuromorphic memory circuit according to one embodiment comprises a plurality of memory cells, wherein each of the plurality of memory cells may generate an output signal in response to the delayed input signal through a first switching element whose critical switching time varies according to a voltage caught to both ends, based on a first resistive memory element.
일 실시예에 따른 뉴로모픽 메모리 회로는 복수의 메모리 셀들(memory cells)을 포함하고, 복수의 메모리 셀들의 각각은, 제1 저항성 메모리 소자에 기초한, 양단에 걸리는 전압에 따라 임계 스위칭 시간이 달라지는 제1 스위칭 소자를 통해 지연된 상기 입력 신호에 응답하여 출력 신호를 생성할 수 있다. |
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