SEMICONDUCTOR PACKAGE
A semiconductor package according to an embodiment of the present invention may include: a circuit board including a wiring structure; first and second semiconductor chips disposed on the circuit board and connected to the wiring structure; a dummy chip disposed on the circuit board and disposed bet...
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| creator | LEE YOUNG MIN KIM DONG KWAN KO JI HAN RYU JUNG SEOK CHANG WON GI |
| description | A semiconductor package according to an embodiment of the present invention may include: a circuit board including a wiring structure; first and second semiconductor chips disposed on the circuit board and connected to the wiring structure; a dummy chip disposed on the circuit board and disposed between the first and second semiconductor chips; and a molding member disposed on the circuit board to surround the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded corner between an upper surface and a side surface. Therefore, it is possible to prevent the visual variation of a surface.
본 발명의 실시예에 따른 반도체 패키지는, 배선 구조물을 포함하는 회로 기판; 상기 회로 기판 상에 배치되며, 상기 배선 구조물과 연결되는 제1 및 제2 반도체 칩; 상기 회로 기판 상에 배치되며, 상기 제1 및 제2 반도체 칩 사이에 배치되는 더미 칩; 및 상기 회로 기판 상에 배치되어 상기 제1 및 제2 반도체 칩과 상기 더미 칩을 둘러싸는 몰딩 부재;를 포함할 수 있다. 상기 더미 칩은, 상면과 측면 사이에 라운드된 모서리를 포함할 수 있다. |
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본 발명의 실시예에 따른 반도체 패키지는, 배선 구조물을 포함하는 회로 기판; 상기 회로 기판 상에 배치되며, 상기 배선 구조물과 연결되는 제1 및 제2 반도체 칩; 상기 회로 기판 상에 배치되며, 상기 제1 및 제2 반도체 칩 사이에 배치되는 더미 칩; 및 상기 회로 기판 상에 배치되어 상기 제1 및 제2 반도체 칩과 상기 더미 칩을 둘러싸는 몰딩 부재;를 포함할 수 있다. 상기 더미 칩은, 상면과 측면 사이에 라운드된 모서리를 포함할 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230323&DB=EPODOC&CC=KR&NR=20230040392A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230323&DB=EPODOC&CC=KR&NR=20230040392A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE YOUNG MIN</creatorcontrib><creatorcontrib>KIM DONG KWAN</creatorcontrib><creatorcontrib>KO JI HAN</creatorcontrib><creatorcontrib>RYU JUNG SEOK</creatorcontrib><creatorcontrib>CHANG WON GI</creatorcontrib><title>SEMICONDUCTOR PACKAGE</title><description>A semiconductor package according to an embodiment of the present invention may include: a circuit board including a wiring structure; first and second semiconductor chips disposed on the circuit board and connected to the wiring structure; a dummy chip disposed on the circuit board and disposed between the first and second semiconductor chips; and a molding member disposed on the circuit board to surround the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded corner between an upper surface and a side surface. Therefore, it is possible to prevent the visual variation of a surface.
본 발명의 실시예에 따른 반도체 패키지는, 배선 구조물을 포함하는 회로 기판; 상기 회로 기판 상에 배치되며, 상기 배선 구조물과 연결되는 제1 및 제2 반도체 칩; 상기 회로 기판 상에 배치되며, 상기 제1 및 제2 반도체 칩 사이에 배치되는 더미 칩; 및 상기 회로 기판 상에 배치되어 상기 제1 및 제2 반도체 칩과 상기 더미 칩을 둘러싸는 몰딩 부재;를 포함할 수 있다. 상기 더미 칩은, 상면과 측면 사이에 라운드된 모서리를 포함할 수 있다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kFGBkbGBgYmBsaWRo7GxKkCABQeH7U</recordid><startdate>20230323</startdate><enddate>20230323</enddate><creator>LEE YOUNG MIN</creator><creator>KIM DONG KWAN</creator><creator>KO JI HAN</creator><creator>RYU JUNG SEOK</creator><creator>CHANG WON GI</creator><scope>EVB</scope></search><sort><creationdate>20230323</creationdate><title>SEMICONDUCTOR PACKAGE</title><author>LEE YOUNG MIN ; KIM DONG KWAN ; KO JI HAN ; RYU JUNG SEOK ; CHANG WON GI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20230040392A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE YOUNG MIN</creatorcontrib><creatorcontrib>KIM DONG KWAN</creatorcontrib><creatorcontrib>KO JI HAN</creatorcontrib><creatorcontrib>RYU JUNG SEOK</creatorcontrib><creatorcontrib>CHANG WON GI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE YOUNG MIN</au><au>KIM DONG KWAN</au><au>KO JI HAN</au><au>RYU JUNG SEOK</au><au>CHANG WON GI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE</title><date>2023-03-23</date><risdate>2023</risdate><abstract>A semiconductor package according to an embodiment of the present invention may include: a circuit board including a wiring structure; first and second semiconductor chips disposed on the circuit board and connected to the wiring structure; a dummy chip disposed on the circuit board and disposed between the first and second semiconductor chips; and a molding member disposed on the circuit board to surround the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded corner between an upper surface and a side surface. Therefore, it is possible to prevent the visual variation of a surface.
본 발명의 실시예에 따른 반도체 패키지는, 배선 구조물을 포함하는 회로 기판; 상기 회로 기판 상에 배치되며, 상기 배선 구조물과 연결되는 제1 및 제2 반도체 칩; 상기 회로 기판 상에 배치되며, 상기 제1 및 제2 반도체 칩 사이에 배치되는 더미 칩; 및 상기 회로 기판 상에 배치되어 상기 제1 및 제2 반도체 칩과 상기 더미 칩을 둘러싸는 몰딩 부재;를 포함할 수 있다. 상기 더미 칩은, 상면과 측면 사이에 라운드된 모서리를 포함할 수 있다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR PACKAGE |
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