INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME
An integrated circuit including standard cells arranged in a plurality of rows is disclosed. The standard cells include a plurality of functional cells implemented as a logic circuit and a plurality of filler cells including at least one pattern among a back end of line (BEOL) pattern, a middle of l...
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| creator | JEONG MIN JAE YU JI SU RIM WOO JIN SEO JAE WOO YOU HYEON GYU DO JUNG HO |
| description | An integrated circuit including standard cells arranged in a plurality of rows is disclosed. The standard cells include a plurality of functional cells implemented as a logic circuit and a plurality of filler cells including at least one pattern among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern. The plurality of pillar cells include first and second pillar cells having different densities of one of the at least one pattern.
복수의 행들에 정렬된 표준 셀들을 포함하는 집적 회로가 개시된다. 상기 표준 셀들은, 로직 회로로 각각 구현되는 복수의 기능 셀들 및 BEOL(Back end of line) 패턴, MOL(Middle of line) 패턴 또는 FEOL(Front end of line) 패턴 중 적어도 하나의 패턴을 포함하는 복수의 필러(Filler) 셀들을 포함한다. 상기 복수의 필러 셀들은 상기 적어도 하나의 패턴 중 어느 하나의 밀도가 상이한 제1 필러 셀 및 제2 필러 셀을 포함한다. |
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복수의 행들에 정렬된 표준 셀들을 포함하는 집적 회로가 개시된다. 상기 표준 셀들은, 로직 회로로 각각 구현되는 복수의 기능 셀들 및 BEOL(Back end of line) 패턴, MOL(Middle of line) 패턴 또는 FEOL(Front end of line) 패턴 중 적어도 하나의 패턴을 포함하는 복수의 필러(Filler) 셀들을 포함한다. 상기 복수의 필러 셀들은 상기 적어도 하나의 패턴 중 어느 하나의 밀도가 상이한 제1 필러 셀 및 제2 필러 셀을 포함한다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230214&DB=EPODOC&CC=KR&NR=20230022059A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230214&DB=EPODOC&CC=KR&NR=20230022059A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JEONG MIN JAE</creatorcontrib><creatorcontrib>YU JI SU</creatorcontrib><creatorcontrib>RIM WOO JIN</creatorcontrib><creatorcontrib>SEO JAE WOO</creatorcontrib><creatorcontrib>YOU HYEON GYU</creatorcontrib><creatorcontrib>DO JUNG HO</creatorcontrib><title>INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME</title><description>An integrated circuit including standard cells arranged in a plurality of rows is disclosed. The standard cells include a plurality of functional cells implemented as a logic circuit and a plurality of filler cells including at least one pattern among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern. The plurality of pillar cells include first and second pillar cells having different densities of one of the at least one pattern.
복수의 행들에 정렬된 표준 셀들을 포함하는 집적 회로가 개시된다. 상기 표준 셀들은, 로직 회로로 각각 구현되는 복수의 기능 셀들 및 BEOL(Back end of line) 패턴, MOL(Middle of line) 패턴 또는 FEOL(Front end of line) 패턴 중 적어도 하나의 패턴을 포함하는 복수의 필러(Filler) 셀들을 포함한다. 상기 복수의 필러 셀들은 상기 적어도 하나의 패턴 중 어느 하나의 밀도가 상이한 제1 필러 셀 및 제2 필러 셀을 포함한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirEKwjAQQLM4iPoPB85CSHFwvCaXJpimcL3OpUicRAv1_7GCH-D0Hry3VTlmoYZRyIGNbIcoELNNg4u5gV4wO-Q1UUqwOrQkoXPgOwaPNUeL8h0lEPTY0l5t7tNjKYcfd-roSWw4lfk1lmWebuVZ3uOVjTaV1sbo8wWr_64PpKIu5w</recordid><startdate>20230214</startdate><enddate>20230214</enddate><creator>JEONG MIN JAE</creator><creator>YU JI SU</creator><creator>RIM WOO JIN</creator><creator>SEO JAE WOO</creator><creator>YOU HYEON GYU</creator><creator>DO JUNG HO</creator><scope>EVB</scope></search><sort><creationdate>20230214</creationdate><title>INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME</title><author>JEONG MIN JAE ; YU JI SU ; RIM WOO JIN ; SEO JAE WOO ; YOU HYEON GYU ; DO JUNG HO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20230022059A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JEONG MIN JAE</creatorcontrib><creatorcontrib>YU JI SU</creatorcontrib><creatorcontrib>RIM WOO JIN</creatorcontrib><creatorcontrib>SEO JAE WOO</creatorcontrib><creatorcontrib>YOU HYEON GYU</creatorcontrib><creatorcontrib>DO JUNG HO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEONG MIN JAE</au><au>YU JI SU</au><au>RIM WOO JIN</au><au>SEO JAE WOO</au><au>YOU HYEON GYU</au><au>DO JUNG HO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME</title><date>2023-02-14</date><risdate>2023</risdate><abstract>An integrated circuit including standard cells arranged in a plurality of rows is disclosed. The standard cells include a plurality of functional cells implemented as a logic circuit and a plurality of filler cells including at least one pattern among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern. The plurality of pillar cells include first and second pillar cells having different densities of one of the at least one pattern.
복수의 행들에 정렬된 표준 셀들을 포함하는 집적 회로가 개시된다. 상기 표준 셀들은, 로직 회로로 각각 구현되는 복수의 기능 셀들 및 BEOL(Back end of line) 패턴, MOL(Middle of line) 패턴 또는 FEOL(Front end of line) 패턴 중 적어도 하나의 패턴을 포함하는 복수의 필러(Filler) 셀들을 포함한다. 상기 복수의 필러 셀들은 상기 적어도 하나의 패턴 중 어느 하나의 밀도가 상이한 제1 필러 셀 및 제2 필러 셀을 포함한다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME |
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