INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME

INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR FABRICATING THE SAME

An integrated circuit including standard cells arranged in a plurality of rows is disclosed. The standard cells include a plurality of functional cells implemented as a logic circuit and a plurality of filler cells including at least one pattern among a back end of line (BEOL) pattern, a middle of l...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: JEONG MIN JAE, YU JI SU, RIM WOO JIN, SEO JAE WOO, YOU HYEON GYU, DO JUNG HO
Format: Patent
Sprache:eng ; kor
Schlagworte:
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An integrated circuit including standard cells arranged in a plurality of rows is disclosed. The standard cells include a plurality of functional cells implemented as a logic circuit and a plurality of filler cells including at least one pattern among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern. The plurality of pillar cells include first and second pillar cells having different densities of one of the at least one pattern. 복수의 행들에 정렬된 표준 셀들을 포함하는 집적 회로가 개시된다. 상기 표준 셀들은, 로직 회로로 각각 구현되는 복수의 기능 셀들 및 BEOL(Back end of line) 패턴, MOL(Middle of line) 패턴 또는 FEOL(Front end of line) 패턴 중 적어도 하나의 패턴을 포함하는 복수의 필러(Filler) 셀들을 포함한다. 상기 복수의 필러 셀들은 상기 적어도 하나의 패턴 중 어느 하나의 밀도가 상이한 제1 필러 셀 및 제2 필러 셀을 포함한다.