Power Management Integrated Circuit and its Driving Method

An embodiment relates to a power management circuit, which comprises: a delay circuit which delays an on-clock signal (ON_CLK), which sets an output start point of a gate driving circuit, or an off-clock signal (OFF_CLK), which sets an initialization point of the gate driving circuit, by a set time and outputs the delayed signal; a multiplexer which selects and outputs one of the delayed signals transmitted from signal lines connected to the delay circuit; and a gate clock generation circuit which generates a gate clock signal (GCLK) by combining the on-clock signal (ON_CLK) and the off-clock signal (OFF_CLK) output from the multiplexer. The present invention can reduce the driving time of the gate driving circuit. 본 실시예는 게이트구동회로의 출력 시작시점을 설정하는 온클럭신호(ON_CLK) 또는 게이트구동회로의 초기화 시점을 설정하는 오프클럭신호(OFF_CLK)를 설정된 시간만큼 지연시켜 출력하는 딜레이회로, 딜레이회로와 연결된 신호라인들에서 전달되는 지연신호들 중 하나를 선택하여 출력하는 멀티플렉서 및 멀티플렉서에서 출력되는 상기 온클럭신호(ON_CLK) 및 상기 오프클럭신호(OFF_CLK)를 조합하여 게이트클럭신호(GCLK)를 생성하는 게이트클럭생성회로를 포함하는 전원관리회로에 관한 것이다.