BUFFER CIRCUIT
A buffer circuit can receive first and second input signals through first and second input transistors connected to a first power supply voltage terminal. A first output signal may be outputted to a first output node and a second output signal may be outputted to a second output node based on the fi...
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| creator | CHANG KYU CHOI DONG UC KO SUNG GIL JANG YANG HO SUR TAE JIN HWANG SUN KI CHO MIN SUNG CHEON JUN YONG SONG HAE KANG JUNG |
| description | A buffer circuit can receive first and second input signals through first and second input transistors connected to a first power supply voltage terminal. A first output signal may be outputted to a first output node and a second output signal may be outputted to a second output node based on the first and second input signals. A load circuit is connected between the first output node, the second output node and a second power supply voltage terminal. A resistance value may be adjusted based on at least one of the first output signal and the second output signal. The buffer circuit comprises: a first input transistor; a second input transistor; and a load circuit.
버퍼 회로는 제 1 전원 전압 단자와 연결되는 제 1 및 제 2 입력 트랜지스터를 통해 제 1 및 제 2 입력 신호를 수신하고, 상기 제 1 및 제 2 입력 신호에 기초하여 제 1 출력 노드로 제 1 출력 신호를 출력하고 제 2 출력 노드로 제 2 출력 신호를 출력할 수 있다. 로드 회로는 상기 제 1 출력 노드, 상기 제 2 출력 노드 및 제 2 전원 전압 단자 사이에 연결되고, 상기 제 1 출력 신호 및 상기 제 2 출력 신호 중 적어도 하나에 기초하여 저항 값이 조절될 수 있다. |
| format | Patent |
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버퍼 회로는 제 1 전원 전압 단자와 연결되는 제 1 및 제 2 입력 트랜지스터를 통해 제 1 및 제 2 입력 신호를 수신하고, 상기 제 1 및 제 2 입력 신호에 기초하여 제 1 출력 노드로 제 1 출력 신호를 출력하고 제 2 출력 노드로 제 2 출력 신호를 출력할 수 있다. 로드 회로는 상기 제 1 출력 노드, 상기 제 2 출력 노드 및 제 2 전원 전압 단자 사이에 연결되고, 상기 제 1 출력 신호 및 상기 제 2 출력 신호 중 적어도 하나에 기초하여 저항 값이 조절될 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220310&DB=EPODOC&CC=KR&NR=20220029900A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220310&DB=EPODOC&CC=KR&NR=20220029900A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG KYU CHOI</creatorcontrib><creatorcontrib>DONG UC KO</creatorcontrib><creatorcontrib>SUNG GIL JANG</creatorcontrib><creatorcontrib>YANG HO SUR</creatorcontrib><creatorcontrib>TAE JIN HWANG</creatorcontrib><creatorcontrib>SUN KI CHO</creatorcontrib><creatorcontrib>MIN SUNG CHEON</creatorcontrib><creatorcontrib>JUN YONG SONG</creatorcontrib><creatorcontrib>HAE KANG JUNG</creatorcontrib><title>BUFFER CIRCUIT</title><description>A buffer circuit can receive first and second input signals through first and second input transistors connected to a first power supply voltage terminal. A first output signal may be outputted to a first output node and a second output signal may be outputted to a second output node based on the first and second input signals. A load circuit is connected between the first output node, the second output node and a second power supply voltage terminal. A resistance value may be adjusted based on at least one of the first output signal and the second output signal. The buffer circuit comprises: a first input transistor; a second input transistor; and a load circuit.
버퍼 회로는 제 1 전원 전압 단자와 연결되는 제 1 및 제 2 입력 트랜지스터를 통해 제 1 및 제 2 입력 신호를 수신하고, 상기 제 1 및 제 2 입력 신호에 기초하여 제 1 출력 노드로 제 1 출력 신호를 출력하고 제 2 출력 노드로 제 2 출력 신호를 출력할 수 있다. 로드 회로는 상기 제 1 출력 노드, 상기 제 2 출력 노드 및 제 2 전원 전압 단자 사이에 연결되고, 상기 제 1 출력 신호 및 상기 제 2 출력 신호 중 적어도 하나에 기초하여 저항 값이 조절될 수 있다.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOBzCnVzcw1ScPYMcg71DOFhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGRkYGBkaWlgYGjsbEqQIAM6Mdsg</recordid><startdate>20220310</startdate><enddate>20220310</enddate><creator>CHANG KYU CHOI</creator><creator>DONG UC KO</creator><creator>SUNG GIL JANG</creator><creator>YANG HO SUR</creator><creator>TAE JIN HWANG</creator><creator>SUN KI CHO</creator><creator>MIN SUNG CHEON</creator><creator>JUN YONG SONG</creator><creator>HAE KANG JUNG</creator><scope>EVB</scope></search><sort><creationdate>20220310</creationdate><title>BUFFER CIRCUIT</title><author>CHANG KYU CHOI ; DONG UC KO ; SUNG GIL JANG ; YANG HO SUR ; TAE JIN HWANG ; SUN KI CHO ; MIN SUNG CHEON ; JUN YONG SONG ; HAE KANG JUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20220029900A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2022</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANG KYU CHOI</creatorcontrib><creatorcontrib>DONG UC KO</creatorcontrib><creatorcontrib>SUNG GIL JANG</creatorcontrib><creatorcontrib>YANG HO SUR</creatorcontrib><creatorcontrib>TAE JIN HWANG</creatorcontrib><creatorcontrib>SUN KI CHO</creatorcontrib><creatorcontrib>MIN SUNG CHEON</creatorcontrib><creatorcontrib>JUN YONG SONG</creatorcontrib><creatorcontrib>HAE KANG JUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANG KYU CHOI</au><au>DONG UC KO</au><au>SUNG GIL JANG</au><au>YANG HO SUR</au><au>TAE JIN HWANG</au><au>SUN KI CHO</au><au>MIN SUNG CHEON</au><au>JUN YONG SONG</au><au>HAE KANG JUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BUFFER CIRCUIT</title><date>2022-03-10</date><risdate>2022</risdate><abstract>A buffer circuit can receive first and second input signals through first and second input transistors connected to a first power supply voltage terminal. A first output signal may be outputted to a first output node and a second output signal may be outputted to a second output node based on the first and second input signals. A load circuit is connected between the first output node, the second output node and a second power supply voltage terminal. A resistance value may be adjusted based on at least one of the first output signal and the second output signal. The buffer circuit comprises: a first input transistor; a second input transistor; and a load circuit.
버퍼 회로는 제 1 전원 전압 단자와 연결되는 제 1 및 제 2 입력 트랜지스터를 통해 제 1 및 제 2 입력 신호를 수신하고, 상기 제 1 및 제 2 입력 신호에 기초하여 제 1 출력 노드로 제 1 출력 신호를 출력하고 제 2 출력 노드로 제 2 출력 신호를 출력할 수 있다. 로드 회로는 상기 제 1 출력 노드, 상기 제 2 출력 노드 및 제 2 전원 전압 단자 사이에 연결되고, 상기 제 1 출력 신호 및 상기 제 2 출력 신호 중 적어도 하나에 기초하여 저항 값이 조절될 수 있다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | BUFFER CIRCUIT |
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