SEMICONDUCTOR PACKAGE
One of the problems to be solved by the present invention is to provide a semiconductor package having improved warpage at room temperature and high temperature. One embodiment of the present invention comprises: a substrate comprising wiring; a semiconductor chip structure disposed on the substrate...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; kor |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | One of the problems to be solved by the present invention is to provide a semiconductor package having improved warpage at room temperature and high temperature. One embodiment of the present invention comprises: a substrate comprising wiring; a semiconductor chip structure disposed on the substrate and electrically connected to the wiring; an underfill resin filling between the substrate and the semiconductor chip structure; and a stiffener surrounding the semiconductor chip structure on the substrate. The stiffener provides a semiconductor package including a conductive frame having a cavity and an insulating filler filling the cavity.
본 발명의 일 실시예는, 배선을 포함하는 기판, 상기 기판 상에 배치되며, 상기 배선에 전기적으로 연결된 반도체 칩 구조물, 상기 기판과 상기 반도체 칩 구조물 사이를 채우는 언더필 수지, 및 상기 기판 상에서, 상기 반도체 칩 구조물을 둘러싸는 스티프너를 포함하되, 상기 스티프너는 캐비티를 갖는 도전성 프레임 및 상기 캐비티를 채우는 절연성 충진재를 포함하는 반도체 패키지를 제공한다. |
|---|