STACKED SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF
The present invention relates to a semiconductor device. The semiconductor device may include: a forcing line formed to be extended from the upper portion of a through electrode in a first direction and electrically connected to the through electrode; first and second monitoring lines spaced apart f...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | The present invention relates to a semiconductor device. The semiconductor device may include: a forcing line formed to be extended from the upper portion of a through electrode in a first direction and electrically connected to the through electrode; first and second monitoring lines spaced apart from the forcing line by a first interval and a second interval in a second direction and a direction opposite to the second direction, respectively, and formed to be extended in the first direction; and a selection circuit for selecting one of the voltage levels of the first monitoring line and the second monitoring line according to a monitoring signal and outputting the selected voltage level as a detection signal. An objective of the present invention is to provide the stacked semiconductor device capable of verifying at a wafer level whether a through electrode is formed in a normal size.
본 발명은 반도체 장치에 관한 것으로, 관통 전극의 상부에서 제 1 방향으로 연장되도록 형성되며, 상기 관통 전극과 전기적으로 연결된 포싱 라인; 상기 포싱 라인으로부터 제 2 방향 및 상기 제 2 방향의 반대 방향으로 제 1 간격 및 제 2 간격으로 각각 이격되어 상기 제 1 방향으로 연장되도록 형성된 제 1 및 제 2 모니터링 라인; 및 모니터링 신호에 따라 상기 제 1 모니터링 라인 및 상기 제 2 모니터링 라인의 전압 레벨 중 하나를 선택하여 검출 신호로 출력하는 선택 회로를 포함할 수 있다. |
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