METHOD FOR MANUFACTURING OF THIN FILM TRANSISTOR

The present invention provides a manufacturing method of a thin film transistor array substrate. The manufacturing method of a thin film transistor array substrate includes the steps of: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a semicond...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	LEE HONG BEOM, KWON CHANG WOO
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	BASIC ELECTRIC ELEMENTS DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FREQUENCY-CHANGING NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS SEMICONDUCTOR DEVICES TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	The present invention provides a manufacturing method of a thin film transistor array substrate. The manufacturing method of a thin film transistor array substrate includes the steps of: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film; forming an ohmic contact layer on the semiconductor layer; and forming a source electrode and a drain electrode including a plurality of metal layer patterns on the ohmic contact layer. Any one of the plurality of metal layer patterns is etched by a polishing process. According to the present invention, stains on the image compared to the wet etching process can be reduced. 본 발명은 박막 트랜지스터 어레이 기판의 제조방법을 제공한다. 박막 트랜지스터 어레이 기판의 제조방법은 기판 상에 게이트 전극을 형성하는 단계, 상기 게이트 전극 상에 게이트 절연막을 형성하는 단계, 상기 게이트 절연막 상에 반도체층을 형성하는 단계, 상기 반도체층 상에 오믹 콘택층을 형성하는 단계, 및 상기 오믹 콘택층 상에 복수의 금속층 패턴을 포함하는 소스 전극 및 드레인 전극을 형성하는 단계를 포함하며, 상기 복수의 금속층 패턴 중 어느 하나는 연마 공정으로 식각한다.