Memory device including processing element and memory system including the memory device
A memory device according to a technical idea of the present disclosure comprises: a memory cell array comprising a plurality of banks; at least one processing element (PE) connected to at least one of the plurality of banks; and a control logic configured to control an active operation of activatin...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | A memory device according to a technical idea of the present disclosure comprises: a memory cell array comprising a plurality of banks; at least one processing element (PE) connected to at least one of the plurality of banks; and a control logic configured to control an active operation of activating at least one of word lines included in each of the plurality of banks and a refresh operation for the plurality of banks based on a PE enable signal to enable at least one PE. Therefore, the present invention is capable of increasing the data operation speed and data operation amount.
본 개시의 기술적 사상에 따른 메모리 장치는, 복수의 뱅크들을 포함하는 메모리 셀 어레이, 복수의 뱅크들 중 적어도 하나에 연결된 적어도 하나의 PE(Processing Element), 및 적어도 하나의 PE를 인에이블시키기 위한 PE 인에이블 신호를 기초로 복수의 뱅크들 각각에 포함된 워드 라인들 중 적어도 하나를 활성화시키는 액티브 동작 및 복수의 뱅크들에 대한 리프레쉬 동작을 제어하도록 구성된 제어 로직을 포함한다. |
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