MEMORY DEVICE AND OPERATING METHOD THEREOF
The present technique relates to an electronic device. A memory device including a plurality of planes includes: a mode setting unit configured to set an operation mode of the memory device as a verification pass mode to pass a verification operation regardless of a result of the verification operat...
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| Hauptverfasser: | , |
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | The present technique relates to an electronic device. A memory device including a plurality of planes includes: a mode setting unit configured to set an operation mode of the memory device as a verification pass mode to pass a verification operation regardless of a result of the verification operation performed on the plurality of planes; and a verification signal generation unit outputting a verification pass signal indicating that the verification operation has been passed for each of the plurality of planes. The memory device of the present invention can control the verification operation for each plane.
본 기술은 전자 장치에 관한 것으로, 복수의 플레인들을 포함하는 메모리 장치에 있어서, 상기 메모리 장치는, 상기 복수의 플레인들에 수행되는 검증 동작의 결과에 관계없이, 상기 검증 동작이 패스되도록하는 상기 메모리 장치의 동작 모드를 검증 패스 모드로 설정하는 모드 설정부 및 상기 복수의 플레인들 마다 상기 검증 동작이 패스되었음을 나타내는 검증 패스 신호를 출력하는 검증 신호 생성부를 포함한다. |
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