Method of manufacturing semiconductor devices
The present invention provides a method of manufacturing a semiconductor device. The method includes the steps of: forming a plurality of via holes on a first substrate; forming a separation layer on an upper surface of the first substrate; growing a first epi layer and a second epi layer on the upp...
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| creator | KYU JUN CHO SUNGJAE CHANG HYUNG SUP YOON SUNG BUM BAE BYOUNG GUE MIN |
| description | The present invention provides a method of manufacturing a semiconductor device. The method includes the steps of: forming a plurality of via holes on a first substrate; forming a separation layer on an upper surface of the first substrate; growing a first epi layer and a second epi layer on the upper surface of the separation layer; forming transistor elements on an upper surface of the second epi layer; providing a solution through the via holes of the first substrate and dissolving the separation layer to separate the first substrate; and bonding a second substrate to the lower surface of the first epi layer.
본 발명은 제 1 기판에 복수개의 비아홀들을 형성하는 단계, 상기 제 1 기판의 상부면에 분리층을 형성하는 단계, 상기 분리층의 상부면에 제 1 에피층 및 제 2 에피층을 성장시키는 단계, 상기 제 2 에피층의 상부면에 트랜지스터 소자들을 형성하는 단계, 상기 제 1 기판의 상기 비아홀들을 통해 용해액을 제공하여 상기 분리층을 용해시킴으로써 상기 제 1 기판을 분리시키는 단계, 및 상기 제 1 에피층의 하부면에 제 2 기판을 접합하는 단계를 포함하는 반도체 소자의 제조 방법을 개시한다. |
| format | Patent |
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본 발명은 제 1 기판에 복수개의 비아홀들을 형성하는 단계, 상기 제 1 기판의 상부면에 분리층을 형성하는 단계, 상기 분리층의 상부면에 제 1 에피층 및 제 2 에피층을 성장시키는 단계, 상기 제 2 에피층의 상부면에 트랜지스터 소자들을 형성하는 단계, 상기 제 1 기판의 상기 비아홀들을 통해 용해액을 제공하여 상기 분리층을 용해시킴으로써 상기 제 1 기판을 분리시키는 단계, 및 상기 제 1 에피층의 하부면에 제 2 기판을 접합하는 단계를 포함하는 반도체 소자의 제조 방법을 개시한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND1TS3JyE9RyE9TyE3MK01LTC4pLcrMS1coTs3NTM7PSylNLskvUkhJLctMTi3mYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kFGBkYGBgZm5uaGRo7GxKkCAJyzK3I</recordid><startdate>20200612</startdate><enddate>20200612</enddate><creator>KYU JUN CHO</creator><creator>SUNGJAE CHANG</creator><creator>HYUNG SUP YOON</creator><creator>SUNG BUM BAE</creator><creator>BYOUNG GUE MIN</creator><scope>EVB</scope></search><sort><creationdate>20200612</creationdate><title>Method of manufacturing semiconductor devices</title><author>KYU JUN CHO ; SUNGJAE CHANG ; HYUNG SUP YOON ; SUNG BUM BAE ; BYOUNG GUE MIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20200067712A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KYU JUN CHO</creatorcontrib><creatorcontrib>SUNGJAE CHANG</creatorcontrib><creatorcontrib>HYUNG SUP YOON</creatorcontrib><creatorcontrib>SUNG BUM BAE</creatorcontrib><creatorcontrib>BYOUNG GUE MIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KYU JUN CHO</au><au>SUNGJAE CHANG</au><au>HYUNG SUP YOON</au><au>SUNG BUM BAE</au><au>BYOUNG GUE MIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing semiconductor devices</title><date>2020-06-12</date><risdate>2020</risdate><abstract>The present invention provides a method of manufacturing a semiconductor device. The method includes the steps of: forming a plurality of via holes on a first substrate; forming a separation layer on an upper surface of the first substrate; growing a first epi layer and a second epi layer on the upper surface of the separation layer; forming transistor elements on an upper surface of the second epi layer; providing a solution through the via holes of the first substrate and dissolving the separation layer to separate the first substrate; and bonding a second substrate to the lower surface of the first epi layer.
본 발명은 제 1 기판에 복수개의 비아홀들을 형성하는 단계, 상기 제 1 기판의 상부면에 분리층을 형성하는 단계, 상기 분리층의 상부면에 제 1 에피층 및 제 2 에피층을 성장시키는 단계, 상기 제 2 에피층의 상부면에 트랜지스터 소자들을 형성하는 단계, 상기 제 1 기판의 상기 비아홀들을 통해 용해액을 제공하여 상기 분리층을 용해시킴으로써 상기 제 1 기판을 분리시키는 단계, 및 상기 제 1 에피층의 하부면에 제 2 기판을 접합하는 단계를 포함하는 반도체 소자의 제조 방법을 개시한다.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Method of manufacturing semiconductor devices |
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