FAN-OUT SEMICONDUCTOR PACKAGE
The present disclosure relates to a fan-out semiconductor package comprising: a semiconductor chip having an active surface on which an access pad is disposed, and an inactive surface opposite to the active surface; a sealing material covering the inactive surface of the semiconductor chip; a therma...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | The present disclosure relates to a fan-out semiconductor package comprising: a semiconductor chip having an active surface on which an access pad is disposed, and an inactive surface opposite to the active surface; a sealing material covering the inactive surface of the semiconductor chip; a thermally conductive via penetrating at least a portion of the sealing material on the inactive surface of the semiconductor chip and physically spaced apart from the inactive surface of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and comprising a redistribution layer electrically connected to the connection pad. According to the present invention, warpage problems and reliability problems can be overcome.
본 개시는 접속패드가 배치된 활성면과 활성면의 반대측인 비활성면을 갖는 반도체칩, 상기 반도체칩의 비활성면을 덮는 봉합재, 상기 반도체칩의 비활성면 상에서 상기 봉합재의 적어도 일부를 관통하되 상기 반도체칩의 비활성면과는 물리적으로 이격된 열전도성 비아, 및 상기 반도체칩의 활성면 상에 배치되며 상기 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결구조체를 포함하는, 팬-아웃 반도체 패키지에 관한 것이다. |
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