MEMORY REDUNDANCY
Disclosed are different embodiments of local redundancy decoder circuits which may be used in a memory device. The different types of local redundancy decoder circuits are operably connected to columns of memory cells in a memory array. A memory device comprises a first column of memory cells, a fir...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | Disclosed are different embodiments of local redundancy decoder circuits which may be used in a memory device. The different types of local redundancy decoder circuits are operably connected to columns of memory cells in a memory array. A memory device comprises a first column of memory cells, a first local redundancy decoder circuit, a second column of memory cells, and a second local redundancy decoder circuit.
메모리 디바이스에 사용될 수 있는 로컬 중복 디코더 회로의 상이한 실시예들이 개시된다. 상이한 유형들의 로컬 중복 디코더 회로들은 메모리 어레이 내의 메모리 셀들의 열들(columns)에 동작 가능하게 접속된다. |
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