SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device comprises: a laminate; a source connection structure penetrating the laminate; n first channel columns positioned on one side of the source connection structure and including channel patterns; and n+k second channel columns positioned on the other side of the source connection...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHOI JUNG DAL, LEE NAM JAE
Format: Patent
Sprache:eng ; kor
Schlagworte:
ELECTRICITY
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHOI JUNG DAL
LEE NAM JAE
description A semiconductor device comprises: a laminate; a source connection structure penetrating the laminate; n first channel columns positioned on one side of the source connection structure and including channel patterns; and n+k second channel columns positioned on the other side of the source connection structure and including channel patterns or dummy channel patterns, wherein n and k may be integers of 1 or more. It is possible to easily manufacture a semiconductor device with a stable structure and improved characteristics. 반도체 장치는 적층물; 상기 적층물을 관통하는 소스 연결 구조; 상기 소스 연결 구조의 일측에 위치되고, 채널 패턴들을 포함하는 n개의 제1 채널 열들; 및 상기 소스 연결 구조의 타측에 위치되고, 채널 패턴들 또는 더미 채널 패턴들을 포함하는 n+k개의 제2 채널 열들을 포함하고, 상기 n, k는 1 이상의 정수일 수 있다.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20190133362A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20190133362A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20190133362A3</originalsourceid><addsrcrecordid>eNrjZDANdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRCPFwDXL1d-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGhpYGhsbGxmZGjsbEqQIAmJYomA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>CHOI JUNG DAL ; LEE NAM JAE</creator><creatorcontrib>CHOI JUNG DAL ; LEE NAM JAE</creatorcontrib><description>A semiconductor device comprises: a laminate; a source connection structure penetrating the laminate; n first channel columns positioned on one side of the source connection structure and including channel patterns; and n+k second channel columns positioned on the other side of the source connection structure and including channel patterns or dummy channel patterns, wherein n and k may be integers of 1 or more. It is possible to easily manufacture a semiconductor device with a stable structure and improved characteristics. 반도체 장치는 적층물; 상기 적층물을 관통하는 소스 연결 구조; 상기 소스 연결 구조의 일측에 위치되고, 채널 패턴들을 포함하는 n개의 제1 채널 열들; 및 상기 소스 연결 구조의 타측에 위치되고, 채널 패턴들 또는 더미 채널 패턴들을 포함하는 n+k개의 제2 채널 열들을 포함하고, 상기 n, k는 1 이상의 정수일 수 있다.</description><language>eng ; kor</language><subject>ELECTRICITY</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191203&amp;DB=EPODOC&amp;CC=KR&amp;NR=20190133362A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191203&amp;DB=EPODOC&amp;CC=KR&amp;NR=20190133362A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHOI JUNG DAL</creatorcontrib><creatorcontrib>LEE NAM JAE</creatorcontrib><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF</title><description>A semiconductor device comprises: a laminate; a source connection structure penetrating the laminate; n first channel columns positioned on one side of the source connection structure and including channel patterns; and n+k second channel columns positioned on the other side of the source connection structure and including channel patterns or dummy channel patterns, wherein n and k may be integers of 1 or more. It is possible to easily manufacture a semiconductor device with a stable structure and improved characteristics. 반도체 장치는 적층물; 상기 적층물을 관통하는 소스 연결 구조; 상기 소스 연결 구조의 일측에 위치되고, 채널 패턴들을 포함하는 n개의 제1 채널 열들; 및 상기 소스 연결 구조의 타측에 위치되고, 채널 패턴들 또는 더미 채널 패턴들을 포함하는 n+k개의 제2 채널 열들을 포함하고, 상기 n, k는 1 이상의 정수일 수 있다.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDANdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRCPFwDXL1d-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGhpYGhsbGxmZGjsbEqQIAmJYomA</recordid><startdate>20191203</startdate><enddate>20191203</enddate><creator>CHOI JUNG DAL</creator><creator>LEE NAM JAE</creator><scope>EVB</scope></search><sort><creationdate>20191203</creationdate><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF</title><author>CHOI JUNG DAL ; LEE NAM JAE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190133362A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2019</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>CHOI JUNG DAL</creatorcontrib><creatorcontrib>LEE NAM JAE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHOI JUNG DAL</au><au>LEE NAM JAE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF</title><date>2019-12-03</date><risdate>2019</risdate><abstract>A semiconductor device comprises: a laminate; a source connection structure penetrating the laminate; n first channel columns positioned on one side of the source connection structure and including channel patterns; and n+k second channel columns positioned on the other side of the source connection structure and including channel patterns or dummy channel patterns, wherein n and k may be integers of 1 or more. It is possible to easily manufacture a semiconductor device with a stable structure and improved characteristics. 반도체 장치는 적층물; 상기 적층물을 관통하는 소스 연결 구조; 상기 소스 연결 구조의 일측에 위치되고, 채널 패턴들을 포함하는 n개의 제1 채널 열들; 및 상기 소스 연결 구조의 타측에 위치되고, 채널 패턴들 또는 더미 채널 패턴들을 포함하는 n+k개의 제2 채널 열들을 포함하고, 상기 n, k는 1 이상의 정수일 수 있다.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; kor
recordid cdi_epo_espacenet_KR20190133362A
source esp@cenet
subjects ELECTRICITY
title SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T09%3A29%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHOI%20JUNG%20DAL&rft.date=2019-12-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20190133362A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true