CLOCK DISTRIBUTOR MINIMIZING SKEW

The present invention relates to a clock distributor for minimizing a skew phenomenon even if a slightly different voltage is applied. Specifically, the present invention relates to a clock distributor for generating and distributing a clock signal on an integrated circuit, including: a plurality of...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	MOON, GYU, HEO, KANG IN, KIM, HYUN SU, KIM, SUNG JIN
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	MOON, GYU HEO, KANG IN KIM, HYUN SU KIM, SUNG JIN
description	The present invention relates to a clock distributor for minimizing a skew phenomenon even if a slightly different voltage is applied. Specifically, the present invention relates to a clock distributor for generating and distributing a clock signal on an integrated circuit, including: a plurality of chips for generating the clock signal; a voltage source for applying a voltage to at least two chips; and a skew suppression unit for reducing a skew phenomenon between a plurality of clock signals generated in the plurality of chips. The skew suppression unit is a clock bus line for connecting the plurality of chips. Accordingly, the present invention can minimize an error due to a clock skew and an asynchronous operation. 본 발명은, 다소 차이가 나는 전압이 인가되더라도 스큐 현상이 최소화될 수 있는 클럭분배기에 관한 것이다. 구체적으로 본 발명은, 집적회로 상에서 클럭 신호를 생성하고 분배하는 클럭분배기에 있어서, 클럭 신호를 생성하는 복수 개의 칩, 상기 적어도 두 개의 칩에 전압을 인가하기 위한 전압 소스, 및 상기 복수 개의 칩에서 생성되는 복수 개의 클럭 신호들간의 스큐(skew) 현상을 저감시키기 위한 스큐억제부,를 포함하되, 상기 스큐억제부는 상기 복수 개의 칩 사이를 서로 연결하는 클럭 버스 라인인 것을 특징으로 하는, 클럭분배기에 관한 것이다.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20180118357A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20180118357A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20180118357A3</originalsourceid><addsrcrecordid>eNrjZFB09vF39lZw8QwOCfJ0Cg3xD1Lw9fTz9PWM8vRzVwj2dg3nYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kFGBoYWBoaGFsam5o7GxKkCALXUI0g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CLOCK DISTRIBUTOR MINIMIZING SKEW</title><source>esp@cenet</source><creator>MOON, GYU ; HEO, KANG IN ; KIM, HYUN SU ; KIM, SUNG JIN</creator><creatorcontrib>MOON, GYU ; HEO, KANG IN ; KIM, HYUN SU ; KIM, SUNG JIN</creatorcontrib><description>The present invention relates to a clock distributor for minimizing a skew phenomenon even if a slightly different voltage is applied. Specifically, the present invention relates to a clock distributor for generating and distributing a clock signal on an integrated circuit, including: a plurality of chips for generating the clock signal; a voltage source for applying a voltage to at least two chips; and a skew suppression unit for reducing a skew phenomenon between a plurality of clock signals generated in the plurality of chips. The skew suppression unit is a clock bus line for connecting the plurality of chips. Accordingly, the present invention can minimize an error due to a clock skew and an asynchronous operation. 본 발명은, 다소 차이가 나는 전압이 인가되더라도 스큐 현상이 최소화될 수 있는 클럭분배기에 관한 것이다. 구체적으로 본 발명은, 집적회로 상에서 클럭 신호를 생성하고 분배하는 클럭분배기에 있어서, 클럭 신호를 생성하는 복수 개의 칩, 상기 적어도 두 개의 칩에 전압을 인가하기 위한 전압 소스, 및 상기 복수 개의 칩에서 생성되는 복수 개의 클럭 신호들간의 스큐(skew) 현상을 저감시키기 위한 스큐억제부,를 포함하되, 상기 스큐억제부는 상기 복수 개의 칩 사이를 서로 연결하는 클럭 버스 라인인 것을 특징으로 하는, 클럭분배기에 관한 것이다.</description><language>eng ; kor</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181031&DB=EPODOC&CC=KR&NR=20180118357A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181031&DB=EPODOC&CC=KR&NR=20180118357A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MOON, GYU</creatorcontrib><creatorcontrib>HEO, KANG IN</creatorcontrib><creatorcontrib>KIM, HYUN SU</creatorcontrib><creatorcontrib>KIM, SUNG JIN</creatorcontrib><title>CLOCK DISTRIBUTOR MINIMIZING SKEW</title><description>The present invention relates to a clock distributor for minimizing a skew phenomenon even if a slightly different voltage is applied. Specifically, the present invention relates to a clock distributor for generating and distributing a clock signal on an integrated circuit, including: a plurality of chips for generating the clock signal; a voltage source for applying a voltage to at least two chips; and a skew suppression unit for reducing a skew phenomenon between a plurality of clock signals generated in the plurality of chips. The skew suppression unit is a clock bus line for connecting the plurality of chips. Accordingly, the present invention can minimize an error due to a clock skew and an asynchronous operation. 본 발명은, 다소 차이가 나는 전압이 인가되더라도 스큐 현상이 최소화될 수 있는 클럭분배기에 관한 것이다. 구체적으로 본 발명은, 집적회로 상에서 클럭 신호를 생성하고 분배하는 클럭분배기에 있어서, 클럭 신호를 생성하는 복수 개의 칩, 상기 적어도 두 개의 칩에 전압을 인가하기 위한 전압 소스, 및 상기 복수 개의 칩에서 생성되는 복수 개의 클럭 신호들간의 스큐(skew) 현상을 저감시키기 위한 스큐억제부,를 포함하되, 상기 스큐억제부는 상기 복수 개의 칩 사이를 서로 연결하는 클럭 버스 라인인 것을 특징으로 하는, 클럭분배기에 관한 것이다.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB09vF39lZw8QwOCfJ0Cg3xD1Lw9fTz9PWM8vRzVwj2dg3nYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kFGBoYWBoaGFsam5o7GxKkCALXUI0g</recordid><startdate>20181031</startdate><enddate>20181031</enddate><creator>MOON, GYU</creator><creator>HEO, KANG IN</creator><creator>KIM, HYUN SU</creator><creator>KIM, SUNG JIN</creator><scope>EVB</scope></search><sort><creationdate>20181031</creationdate><title>CLOCK DISTRIBUTOR MINIMIZING SKEW</title><author>MOON, GYU ; HEO, KANG IN ; KIM, HYUN SU ; KIM, SUNG JIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20180118357A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2018</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>MOON, GYU</creatorcontrib><creatorcontrib>HEO, KANG IN</creatorcontrib><creatorcontrib>KIM, HYUN SU</creatorcontrib><creatorcontrib>KIM, SUNG JIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MOON, GYU</au><au>HEO, KANG IN</au><au>KIM, HYUN SU</au><au>KIM, SUNG JIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CLOCK DISTRIBUTOR MINIMIZING SKEW</title><date>2018-10-31</date><risdate>2018</risdate><abstract>The present invention relates to a clock distributor for minimizing a skew phenomenon even if a slightly different voltage is applied. Specifically, the present invention relates to a clock distributor for generating and distributing a clock signal on an integrated circuit, including: a plurality of chips for generating the clock signal; a voltage source for applying a voltage to at least two chips; and a skew suppression unit for reducing a skew phenomenon between a plurality of clock signals generated in the plurality of chips. The skew suppression unit is a clock bus line for connecting the plurality of chips. Accordingly, the present invention can minimize an error due to a clock skew and an asynchronous operation. 본 발명은, 다소 차이가 나는 전압이 인가되더라도 스큐 현상이 최소화될 수 있는 클럭분배기에 관한 것이다. 구체적으로 본 발명은, 집적회로 상에서 클럭 신호를 생성하고 분배하는 클럭분배기에 있어서, 클럭 신호를 생성하는 복수 개의 칩, 상기 적어도 두 개의 칩에 전압을 인가하기 위한 전압 소스, 및 상기 복수 개의 칩에서 생성되는 복수 개의 클럭 신호들간의 스큐(skew) 현상을 저감시키기 위한 스큐억제부,를 포함하되, 상기 스큐억제부는 상기 복수 개의 칩 사이를 서로 연결하는 클럭 버스 라인인 것을 특징으로 하는, 클럭분배기에 관한 것이다.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng ; kor
recordid	cdi_epo_espacenet_KR20180118357A
source	esp@cenet
subjects	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
title	CLOCK DISTRIBUTOR MINIMIZING SKEW
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T07%3A59%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MOON,%20GYU&rft.date=2018-10-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20180118357A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true