Computer-implemented method for designing integrated circuit

A computer implementing method for designing an integrated circuit according to the present disclosure includes the steps of: receiving first data which includes a plurality of resistance values for vias included in the integrated circuit, wherein each of the plurality of resistance values is define...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: OH, SUNG MIN, JEONG, KWANG OK, KANG, JONG KU
Format: Patent
Sprache:eng ; kor
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A computer implementing method for designing an integrated circuit according to the present disclosure includes the steps of: receiving first data which includes a plurality of resistance values for vias included in the integrated circuit, wherein each of the plurality of resistance values is defined by at least one of a width of a conductive line connected to the via and a space between the conductive line and an adjacent conductive line; receiving second data including physical information about a layout of the integrated circuit; and extracting via resistance according to the layout among the plurality of resistance values based on the first data and the second data by using a processor. Accordingly, the present invention can dynamically extract a parasitic component of the via. 본 개시에 따른 집적 회로를 설계하기 위한 컴퓨터 구현 방법은, 집적 회로에 포함되는 비아에 대한 복수의 저항 값들을 포함하고, 복수의 저항 값들의 각각은 비아에 연결되는 도전 라인의 너비 및 도전 라인과 인접 도전 라인 사이의 스페이스 중 적어도 하나에 따라 정의되는, 제1 데이터를 수신하고, 집적 회로의 레이아웃에 대한 물리적 정보를 포함하는 제2 데이터를 수신하며, 프로세서를 이용하여 제1 및 제2 데이터를 기초로 복수의 저항 값들 중 레이아웃에 따른 비아 저항을 추출한다.