Method for manufacturing semiconductor package

A method for manufacturing a semiconductor package according to a technical idea of the present invention includes the steps of: preparing a package substrate on which a semiconductor chip mounting region is formed; mounting a semiconductor chip on the semiconductor chip mounting region; forming a d...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KANG, CHANG KUN, HAN, SEONG CHAN, LEE, CHIL HOON, LEE, YOUNG ROCK, KIM, HAN JU
Format: Patent
Sprache:eng ; kor
Schlagworte:
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Beschreibung
Zusammenfassung:A method for manufacturing a semiconductor package according to a technical idea of the present invention includes the steps of: preparing a package substrate on which a semiconductor chip mounting region is formed; mounting a semiconductor chip on the semiconductor chip mounting region; forming a dam with a first solution whose temperature is lower than a set first temperature to surround the semiconductor chip; and filling a region defined by the lower side of the semiconductor chip and the dam with an underfill using the first solution at a temperature equal to or higher than the set first temperature. Accordingly, the present invention can improve connection reliability and reduce the defect of the semiconductor package by preventing the leakage of the underfill. 본 발명의 기술적 사상에 의한 반도체 패키지 제조 방법은, 반도체 칩 실장 영역이 형성된 패키지 기판을 준비하는 단계, 반도체 칩 실장 영역에 반도체 칩을 실장하는 단계, 반도체 칩을 둘러싸도록 설정된 제1 온도 미만의 제1 용액으로 댐을 형성하는 단계, 및 반도체 칩의 하부 및 댐에 의하여 한정되는 영역에 설정된 제1 온도 이상의 제1 용액으로 언더필을 충전하는 단계를 포함하는 것을 특징으로 한다.