METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD

The present invention relates to a method for manufacturing a circuit substrate. According to the present invention, a first copper foil is formed on a surface of a first insulation layer based on a predetermined circuit pattern, or is formed under the first insulation layer by using an ETS method....

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KO, YOUNG JOO, LEE, MIN WOO
Format: Patent
Sprache:eng ; kor
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Beschreibung
Zusammenfassung:The present invention relates to a method for manufacturing a circuit substrate. According to the present invention, a first copper foil is formed on a surface of a first insulation layer based on a predetermined circuit pattern, or is formed under the first insulation layer by using an ETS method. A surface of the first copper foil, i.e., belonging to a region in which a cavity is to be formed, is covered with an alkali etch resistant thin film, and a copper plating layer is formed thereon, thereby defining a cavity region. Subsequently, a second insulation layer and a second copper foil are stacked thereon, and the second copper foil is etched based on a predetermined circuit pattern so that a surface of the second insulation layer corresponding to the cavity region is opened. An appearance of the cavity is formed through a drilling process, and holes are drilled at locations in the second insulation layer. Accordingly, an alkali etchant penetrates into the copper plating layer disposed under the second insulation layer through the holes when the alkali etchant is sprayed on the second insulation layer, and the copper plating layer is etched, thereby forming the cavity. In this case, the alkali etch resistant thin film prevents the first copper foil disposed under the cavity from being etched by the etchant, and the first copper foil disposed under the cavity forms a solder junction with a chip terminal when a chip is mounted. 본 발명은 소정의 회로패턴에 따라 제1 절연층 표면에 또는 ETS 공법으로 제1 절연층 속으로 매립해서 제1 동박을 형성한 후, 나중에 캐비티를 형성할 영역에 속해 있는 제1 동박에 대해 표면에 알칼리 식각레지스트 피막을 피복한 후 동도금층을 형성함으로써 캐비티 영역을 정의한다. 이어서, 제2 절연층과 제2 동박을 적층 성형하고, 제2 동박을 소정의 회로패턴에 따라 식각하되 캐비티 영역에 대응하는 제2 절연층 표면이 개구되도록 식각한다. 그리고 나면, 드릴공정으로 캐비티를 외형 가공한 후, 드릴로 상지 제2 절연층을 군데군데 천공하여 홀을 형성함으로써 알칼리 식각액을 스프레이 할 경우, 알칼리 식각액이 홀을 통해 하부의 동도금층으로 침투해서 동도금층을 식각 제거함으로써 캐비티를 제작한다. 이때에, 캐비티 하부의 제1 동박은 알칼리 에치레지스트 피막에 의해 식각용액의 공격으로부터 보호되고, 캐비티 하부의 제1동박은 칩 실장 시에 칩 단자와 솔더 접합을 이루게 된다.