DUMMY CHIP PACKAGE METHOD FOR PREPARING THE SAME AND METHOD FOR TESTING BUMP GAP FILLING AND VOID-FORMATION WITH THE SAME

The present invention relates to a dummy chip package including: a dummy chip including a dummy chip body part and a bump formed in the lower portion of the dummy chip body part; and a substrate formed in the lower portion of the bump. A gap between the dummy chip body part and the substrate is seal...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	NA, WOO CHUL, PARK, SUNG SU, SEO, KYOUNG SEONG, KIM, JAE HYUN, LEE, EUN JUNG
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	The present invention relates to a dummy chip package including: a dummy chip including a dummy chip body part and a bump formed in the lower portion of the dummy chip body part; and a substrate formed in the lower portion of the bump. A gap between the dummy chip body part and the substrate is sealed by means of an epoxy molding compound, thereby testing bump gap filling of a gap between the bumps and a void formation status in real time. 본 발명은 더미 칩 몸체부 및 상기 더미 칩 몸체부 하부에 형성된 범프를 포함하는 더미 칩; 및 상기 범프 하부에 형성된 기판; 을 포함하고, 상기 더미 칩 몸체부와 상기 기판 사이의 갭이 에폭시 몰딩 컴파운드로 밀봉된 것을 특징으로 하는 더미 칩 패키지에 관한 발명으로 범프 사이의 갭의 밀봉(Bump Gap Filling) 및 공극(Void) 형성 여부에 대해 실시간으로 평가할 수 있다.