PROGRAMMABLE FREQUENCY RANGE FOR BOOST CONVERTER CLOCKS

Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst / T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking / delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks.