CONVERTING CONDITIONAL SHORT FORWARD BRANCHES TO COMPUTATIONALLY EQUIVALENT PREDICATED INSTRUCTIONS

A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The conditional short forward branch includes a conditional branch instruction and a set of one or more instructions that sequentially follow the conditional branch instruction in program order. The set of the one or more instructions exists between the conditional branch instruction and a forward branch target instruction that is indicated by the conditional branch instruction. The processor also includes instruction conversion logic connected with the instruction fetch logic. The instruction conversion logic is to convert the conditional short forward branch to a computationally equivalent set of one or more predicated instructions. Other processors are also disclosed in various methods and systems.