SOURCE LINE FLOATING CIRCUIT, MEMORY DEVICE AND METHOD OF READING DATA USING THE SAME

A memory device comprises a memory cell array, a row select circuit and a source line floating circuit. Memory cells aligned in the memory cell array are combined between source lines and bit-lines, and are selected by word lines in a row unit. The row select circuit generates address signal of decoded rows based on row address signals and enables a single select word line among the word lines based on the address signals of the decoded rows. During read operation, the source line floating circuit connects one select source line combined to memory cells selected by the select word line among source lines to ground voltage and floats non-select source lines except for the select source lines by blocking the non-select source lines from the ground voltage.