MEMORY CONTROLLER AND ELECTRONIC DEVICE HAVING THE MEMORY CONTROLLER

Provided is a memory controller capable of controlling a plurality of planes of a nonvolatile memory device to perform an operating command at the same time. The memory controller comprises: a host interface configured to receive, from a host, a first operating command and a plurality of plane logic information of a memory device; a microprocessor configured to decode the first operating command into a second operating command and map the plane logic information to the memory device; a register configured to queue the second operating command and the mapped plane logic information; a memory interface configured to provide the second operating command and the queued plane logic information to the memory device; and a plane control unit configured to control a plurality of planes corresponding to the mapped plane logic information to perform the second operating command at the same time in the memory device.