MEMORY DEVICE

A memory device according to the embodiment of the present invention includes: a plurality of memory cells which are connected to a bit line and a complementary bit line; and a precharge-equalizing unit which precharges and equalizes the bit line and the complementary bit line to perform writing or reading operations on the memory cells. The precharge-equalizing unit includes a plurality of transistors which have active regions in a first direction, are connected to the bit line or the complementary bit line through one end thereof, and share a first gate line which is formed in the first direction.